Y. Yusoff, Hanif Che Lah, N. Razali, Siti Noor Harun, T. Yew
{"title":"带隙电压基准的设计与表征","authors":"Y. Yusoff, Hanif Che Lah, N. Razali, Siti Noor Harun, T. Yew","doi":"10.1109/SMELEC.2012.6417236","DOIUrl":null,"url":null,"abstract":"This paper presents the design and characterization of 1.8V bandgap voltage reference fabricated using Siltera's 0.18um CMOS process technology. The proposed bandgap voltage reference employed two-stage amplifier, start-up and power down circuit. The paper focuses on circuit analysis using SPECTRE and Monte Carlo, layout design technique for reducing mismatch and silicon characterization. The result shows the designed bandgap voltage reference generates a stable voltage reference at 1.204V with average temperature coefficient of 6.5ppm/oC. The power dissipation for this bandgap voltage reference is 150uW under 1.8V supply voltage and it occupies silicon area of 370um×300um.","PeriodicalId":210558,"journal":{"name":"2012 10th IEEE International Conference on Semiconductor Electronics (ICSE)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":"{\"title\":\"Design and characterization of bandgap voltage reference\",\"authors\":\"Y. Yusoff, Hanif Che Lah, N. Razali, Siti Noor Harun, T. Yew\",\"doi\":\"10.1109/SMELEC.2012.6417236\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents the design and characterization of 1.8V bandgap voltage reference fabricated using Siltera's 0.18um CMOS process technology. The proposed bandgap voltage reference employed two-stage amplifier, start-up and power down circuit. The paper focuses on circuit analysis using SPECTRE and Monte Carlo, layout design technique for reducing mismatch and silicon characterization. The result shows the designed bandgap voltage reference generates a stable voltage reference at 1.204V with average temperature coefficient of 6.5ppm/oC. The power dissipation for this bandgap voltage reference is 150uW under 1.8V supply voltage and it occupies silicon area of 370um×300um.\",\"PeriodicalId\":210558,\"journal\":{\"name\":\"2012 10th IEEE International Conference on Semiconductor Electronics (ICSE)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2012-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"7\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2012 10th IEEE International Conference on Semiconductor Electronics (ICSE)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SMELEC.2012.6417236\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 10th IEEE International Conference on Semiconductor Electronics (ICSE)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SMELEC.2012.6417236","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Design and characterization of bandgap voltage reference
This paper presents the design and characterization of 1.8V bandgap voltage reference fabricated using Siltera's 0.18um CMOS process technology. The proposed bandgap voltage reference employed two-stage amplifier, start-up and power down circuit. The paper focuses on circuit analysis using SPECTRE and Monte Carlo, layout design technique for reducing mismatch and silicon characterization. The result shows the designed bandgap voltage reference generates a stable voltage reference at 1.204V with average temperature coefficient of 6.5ppm/oC. The power dissipation for this bandgap voltage reference is 150uW under 1.8V supply voltage and it occupies silicon area of 370um×300um.