用于FOWLP应用的聚合物层间介电体表面平面化

Soo-Geon Kang, Yejin Kim, Ayoung Moon, Sangwon Lee, S. Kim, Sungdong Kim
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引用次数: 3

摘要

聚合物层间介电体的表面平面度是影响扇出式晶圆级封装多级互连的关键因素。聚合物层间介质的表面形貌与下伏金属图案有关,平面化程度越高,线越窄,空间越大。提出了压平表面波动的方法。在软焙过程中,采用压板对PBO表面进行压制,表面平整度得到了有效提高。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Surface Planarization of Polymeric Interlayer Dielectrics for FOWLP Applications
The surface planarity of polymeric interlayer dielectrics becomes a key factor for the multi-level interconnection for fan-out wafer level package. The surface topography of polymeric interlayer dielectrics depends on the underlying metal patterns, and the higher degree of planarization was observed with narrower line and larger space. The pressing method is proposed to flatten the surface undulations. The surface of PBO was pressed with a pressing plate during the soft-bake process, and the surface planarity was observed to be improved effectively.
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