{"title":"155.52 Mb/s双绞线收发器","authors":"M. Altmann, B. Guay","doi":"10.1109/BIPOL.1995.493888","DOIUrl":null,"url":null,"abstract":"An integrated 155 Mb/s twisted pair transceiver with linear pulse shaping and equalization filters, clock recovery, and digital data decoding is implemented in a 0.8 /spl mu/m BiCMOS process. Die area is 18.4 k mil/sup 2/, with P/sub DISS/ of 1.3 W at 5 V.","PeriodicalId":230944,"journal":{"name":"Proceedings of Bipolar/Bicmos Circuits and Technology Meeting","volume":"4 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"A 155.52 Mb/s BiCMOS twisted-pair transceiver\",\"authors\":\"M. Altmann, B. Guay\",\"doi\":\"10.1109/BIPOL.1995.493888\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"An integrated 155 Mb/s twisted pair transceiver with linear pulse shaping and equalization filters, clock recovery, and digital data decoding is implemented in a 0.8 /spl mu/m BiCMOS process. Die area is 18.4 k mil/sup 2/, with P/sub DISS/ of 1.3 W at 5 V.\",\"PeriodicalId\":230944,\"journal\":{\"name\":\"Proceedings of Bipolar/Bicmos Circuits and Technology Meeting\",\"volume\":\"4 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1995-10-02\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of Bipolar/Bicmos Circuits and Technology Meeting\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/BIPOL.1995.493888\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of Bipolar/Bicmos Circuits and Technology Meeting","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/BIPOL.1995.493888","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
An integrated 155 Mb/s twisted pair transceiver with linear pulse shaping and equalization filters, clock recovery, and digital data decoding is implemented in a 0.8 /spl mu/m BiCMOS process. Die area is 18.4 k mil/sup 2/, with P/sub DISS/ of 1.3 W at 5 V.
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