Application of exhaustive search, branch and bound, parallel computing and Monte-Carlo methods for the synthesis of quasi-optimal network-on-chip topologies

On the basis of an integrated network-on-chip (NoC) topologies optimality criterion, as well as applying the adjacency matrix to describe NoC topologies, exhaustive search method and its modification by using branch and bound and Monte-Carlo methods are extended to the synthesis of NoC quasi-optimal topologies. Designed ScaNoC suboptimal topology synthesis algorithm is implemented on a high-level programming language which makes it possible to generate quasi-optimal topological solutions in accordance with the requirements to reduce hardware costs and the average distance between nodes. Proposed quasioptimal topologies synthesis algorithm improvement by using the method of parallel computing allows speeding up the process of synthesis to 2117 times and getting topologies with the number of nodes up to 18.