使用压力测试数据预测系统级故障的统计技术

Harry H. Chen, Shih-Hua Kuo, Jonathan Tung, M. Chao
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引用次数: 8

摘要

本文提出了一种收集和分析芯片故障信号的新方案。在非破坏性应力条件下应用扫描模式会导致数字芯片输出错误。从以持续故障模式收集的二进制错配响应中,通过对每组错配进行分组和计数,形成数字数据特征,从而定义芯片的“模拟”故障特征。我们使用机器学习来探索系统级测试(SLT)故障的预测模型,通过比较来自已知SLT通过/失败箱的芯片样本的特征。明确区分SLT通过/失败芯片的重要特性。给出了一种28纳米1.2 ghz四核低功耗处理器的实验结果。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Statistical techniques for predicting system-level failure using stress-test data
In this paper we describe a novel scheme for collecting and analyzing a chip's failure signature. Incorrect outputs of digital chips are forced by applying scan patterns under non-destructive stress conditions. From binary mismatch responses collected in continue-on-fail mode, numeric data features are formed by grouping and counting mismatches in each group, thus defining a chip's “analog” failure signature. We use machine learning to explore prediction models of system-level test (SLT) failures by comparing signatures of chip samples from known SLT pass/fail bins. Important features that clearly separate the SLT pass/fail chips are identified. Experimental results are presented for a 28-nm 1.2-GHz quad-core low-power processor.
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