Design and analysis of a high-speed channel for Coded Differential signaling

This paper introduces the design and analysis of a high-speed channel for a new signaling scheme called Coded Differential signaling. The coding scheme is designed in such a way that the parallel interface preserves many of the attractive properties of a differential link such as low supply noise generation and immunity to common-mode noise. In addition, the coding completely eliminates the first post-cursor intersymbol interference of the channel over the entire unit-interval at no loss in throughput. As a result, Coded Differential signaling leads to substantial increase in timing margin compared to a differential link with 1-tap post-cursor equalizer, consequently without the associated complexity. The design of the channel, however, requires an innovative approach to optimize the performance and cost of the system. The theory of Coded Differential signaling, the minimization of the timing skew in the channel, and the details of the implementation of a prototype system developed based on proposed scheme for graphics memory interfaces are described in this paper. On-scope measured eye diagrams indicate 30% improvement in timing margin compared to a 1-tap predictive decision feedback equalizer system.