芯片级封装CMOS成像仪键合垫优化

2006 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits Pub Date : 2006-07-03 DOI:10.1109/IPFA.2006.251037

R. J. Rassel, W. Guthrie, J. Gambino, J. Maloney, M. Stidham, E. Sprogis, J. Adkisson, M. Jaffe

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引用次数: 0

摘要

分析了采用0.18 μ m CMOS图像传感器Cu互连技术的三种新型CSP衬垫设计，并将其与晶圆级CSP (WLCSP)封装结合使用。CSP衬垫的设计采用了铝和钨互连层的各种组合，以提高截面积，而不增加铜互连技术的总堆叠高度。研究发现，通过增加CSP焊盘的截面积，CSP过程中形成的t型连接改善了(更紧密)电阻分布

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Bond Pad Optimization for CMOS Imager with Chip Scale Package

Three novel CSP pad designs in a 0.18mum CMOS image sensor Cu interconnect technology were analyzed for use with a wafer level CSP (WLCSP) package. The CSP pad designs used various combinations of available aluminum and tungsten interconnect levels in order to improve the cross-sectional area without increasing the total stack height of the Cu interconnect technology. It was found that by increasing the cross-sectional area of the CSP pads the T-connections formed in the CSP process had improved (tighter) resistance distributions

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2006 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits

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