Simulation of stress distribution in assembled silicon dies and deflection of printed circuit boards

The knowledge of thermally induced strains created during the assembly in Printed Circuit Boards (PCB) is an important issue for electronic packages. In the assembly process, a thin silicon-chip is attached onto a copper foil. The curing of the adhesive is followed by the cooling down of the assembled structure to room temperature. The different properties of the involved materials and the geometry of the structure induce stresses and deflection in the substrate, which can become critical for the further lamination process. In this work, the chip assembly process is investigated by means of a parametric FE analysis. The aim is to estimate the stress distribution in the silicon die and the deflection (warpage) of the entire architecture based on the assembly conditions. The key material properties (i.e. thermal expansion coefficient (CTE) and elastic constants) of all involved materials were determined as a function of the temperature (process relevant temperature up to 200°C) and used as input for the FE model. Special attention has been given to the determination of the volumetric shrinkage of the adhesive during the curing. The results predicted by the FE model are validated with experimental measurements using an X-ray diffraction method (Rocking-Curve-Technique), which enables the deflection of the attached silicon die to be determined. Good agreement between simulation and experiments is achieved.