RISC系统缓存性能的早期系统分析

J. D. Roberts, W. Dai
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引用次数: 7

摘要

封装和互连技术对精简指令集计算(RISC)微处理器内存层次结构的影响进行了检查。之前的早期分析工具要么考虑缓存性能,要么考虑互连模型。在这里,这些分析结合并扩展到更具体的RISC微处理器缓存系统。由此产生的一阶模型允许在设计的预先列表阶段对权衡进行交互式调查。在总结了模型之后,提出了几个测试用例来说明趋势并开始量化设计权衡。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Early system analysis of cache performance for RISC systems
The implications of packaging and interconnection technologies for reduced instruction set computing (RISC) microprocessor memory hierarchies are examined. Prior early analysis tools have taken either cache performance or interconnection models into consideration. Here such analyses are combined and extended to be more specific to RISC microprocessor cache systems. The resulting first-order model allows interactive investigation of tradeoffs at prenetlist phases of design. After summarizing the model, several test cases are presented which illustrate trends and begin to quantify design tradeoffs.<>
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