{"title":"RISC系统缓存性能的早期系统分析","authors":"J. D. Roberts, W. Dai","doi":"10.1109/MCMC.1992.201466","DOIUrl":null,"url":null,"abstract":"The implications of packaging and interconnection technologies for reduced instruction set computing (RISC) microprocessor memory hierarchies are examined. Prior early analysis tools have taken either cache performance or interconnection models into consideration. Here such analyses are combined and extended to be more specific to RISC microprocessor cache systems. The resulting first-order model allows interactive investigation of tradeoffs at prenetlist phases of design. After summarizing the model, several test cases are presented which illustrate trends and begin to quantify design tradeoffs.<<ETX>>","PeriodicalId":202574,"journal":{"name":"Proceedings 1992 IEEE Multi-Chip Module Conference MCMC-92","volume":"35 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1992-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":"{\"title\":\"Early system analysis of cache performance for RISC systems\",\"authors\":\"J. D. Roberts, W. Dai\",\"doi\":\"10.1109/MCMC.1992.201466\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The implications of packaging and interconnection technologies for reduced instruction set computing (RISC) microprocessor memory hierarchies are examined. Prior early analysis tools have taken either cache performance or interconnection models into consideration. Here such analyses are combined and extended to be more specific to RISC microprocessor cache systems. The resulting first-order model allows interactive investigation of tradeoffs at prenetlist phases of design. After summarizing the model, several test cases are presented which illustrate trends and begin to quantify design tradeoffs.<<ETX>>\",\"PeriodicalId\":202574,\"journal\":{\"name\":\"Proceedings 1992 IEEE Multi-Chip Module Conference MCMC-92\",\"volume\":\"35 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1992-03-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"7\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings 1992 IEEE Multi-Chip Module Conference MCMC-92\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/MCMC.1992.201466\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings 1992 IEEE Multi-Chip Module Conference MCMC-92","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MCMC.1992.201466","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Early system analysis of cache performance for RISC systems
The implications of packaging and interconnection technologies for reduced instruction set computing (RISC) microprocessor memory hierarchies are examined. Prior early analysis tools have taken either cache performance or interconnection models into consideration. Here such analyses are combined and extended to be more specific to RISC microprocessor cache systems. The resulting first-order model allows interactive investigation of tradeoffs at prenetlist phases of design. After summarizing the model, several test cases are presented which illustrate trends and begin to quantify design tradeoffs.<>