Electrical-thermal-structural performance of packaged power terminals for wafer baking

Failures may often occur in the packaged power terminals (PPTs) of the heater modules during harsh wafer baking process. The dominant failure factor is a high temperature. Hence, the performances of the PPTs should be explored under multiphysics environment to develop robust heater modules. In this study, FEA electrical-thermal-structural models of the PPTs are developed and experimentally validated. Various parametric influences on the thermal and structural performance of PPTs are investigated employing FEA electrical-thermal-structural models. The study has shown that the substrate thickness was a dominant parameter affecting the PPT performance.