集成电路设计极限的评估

1998 International Semiconductor Conference. CAS'98 Proceedings (Cat. No.98TH8351) Pub Date : 1998-10-06 DOI:10.1109/SMICND.1998.732368

A. Andonova, D.T. Savov

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引用次数: 1

摘要

本文提出了一种评估集成电路设计极限的方法。该方法的基础是对少量测试项目进行破坏性评估，以测量其设计极限。应用结果表明，该方法在ALT实验中是非常有效的。

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Evaluation of integrated circuit's design limits

This paper presents an approach to evaluate the design limits of integrated circuits. The basis of that approach is a destructive evaluation performed on a small number of test items to measure their design limits. Results from applying it demonstrate that the approach can be quite effective for ALT experiments.

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来源期刊

1998 International Semiconductor Conference. CAS'98 Proceedings (Cat. No.98TH8351)

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