High Level Synthesis Of Globally Asynchronous Locally Synchronous Circuits

This paper presents an approach for the design of Globally Asynchronous Locally Synchronous (GALS) circuits, The mixed style using asynchronous and synchronous circuits amalgamates the both styles best features. A language for high level specification of circuits is described. Then, the synthesis method that maps the algorithmic level specification In a net of GALS circuits is given. The a-synchronous part is highlighted and avoidance of metastabiity is described Fin~y, the link to existing CAD tools is given via VHDL.