D. Cai, Houpeng Chen, Xi Li, Qian Wang, Zhitang Song
{"title":"基于40nm技术的128Mb PCRAM电路设计","authors":"D. Cai, Houpeng Chen, Xi Li, Qian Wang, Zhitang Song","doi":"10.1109/NVMTS.2011.6137087","DOIUrl":null,"url":null,"abstract":"In this paper, a 128Mb phase change random access memory based on phase change Ge2Sb2Te5 alloy has been designed in 40nm 4 metal level CMOS technology. Memory cell is the dual trench epitaxial pn junction diode. According to the feature of the 1D1R memory cell structure, array architecture and chip architecture have been optimized. The read access time is 30ns in simulation. The layout area is 6.6mm × 3.8mm.","PeriodicalId":197829,"journal":{"name":"2011 11th Annual Non-Volatile Memory Technology Symposium Proceeding","volume":"22 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Circuit design for 128Mb PCRAM based on 40nm technology\",\"authors\":\"D. Cai, Houpeng Chen, Xi Li, Qian Wang, Zhitang Song\",\"doi\":\"10.1109/NVMTS.2011.6137087\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, a 128Mb phase change random access memory based on phase change Ge2Sb2Te5 alloy has been designed in 40nm 4 metal level CMOS technology. Memory cell is the dual trench epitaxial pn junction diode. According to the feature of the 1D1R memory cell structure, array architecture and chip architecture have been optimized. The read access time is 30ns in simulation. The layout area is 6.6mm × 3.8mm.\",\"PeriodicalId\":197829,\"journal\":{\"name\":\"2011 11th Annual Non-Volatile Memory Technology Symposium Proceeding\",\"volume\":\"22 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2011-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2011 11th Annual Non-Volatile Memory Technology Symposium Proceeding\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/NVMTS.2011.6137087\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 11th Annual Non-Volatile Memory Technology Symposium Proceeding","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/NVMTS.2011.6137087","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Circuit design for 128Mb PCRAM based on 40nm technology
In this paper, a 128Mb phase change random access memory based on phase change Ge2Sb2Te5 alloy has been designed in 40nm 4 metal level CMOS technology. Memory cell is the dual trench epitaxial pn junction diode. According to the feature of the 1D1R memory cell structure, array architecture and chip architecture have been optimized. The read access time is 30ns in simulation. The layout area is 6.6mm × 3.8mm.
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