A New Failure Mechanism of Inter Layer Dielectric Crack

Converting gold wire to copper wire for IC packaging is a big trend recently which has both advantage and disadvantage. Cu wire is good for packaging cost saving to current semiconductor industry, but it may also create quality and reliability issues. Since Cu is much harder and stiffer material than Au, it may require a greater force and USG power to insure good bonding to pad, and a larger bond force and USG power in turn increases the risk of ILD crack during the bonding process. The wafer tech in this study is CMOS40nm, Al thickness is 28KA, with 53um pad opening. The ILD crack mechanism which is discussed in this paper is different. The failure mode during ATE test is leakage failure. After de-cap and cratering test, there is no cratering / damage on failed pad under microscope check. FIB was performed on failed pad and confirmed the damage between Metal 2 and Metal 3, and no damage on top metal. The link between IV curve trace and ILD crack was studied. The root cause of the ILD crack was studied, material and machine variation were also take into consideration. Parameter optimization DOE was done. Key wire bond parameters include the initial force, USG power etc. The wire pull, ball shear, IMC, Al remnant etc. are key response. The result shows that lower USG and higher initial force can get better wire bond performance. The die was packaged into a MAPBGA package. Electrical test was performed on the assembled parts at T0, post MSL3/260degree C, post 264h UHST $(110 ^{\circ}\mathrm{C} /85$%RH), and post TC700cycles ($- 55 ^{\circ}\mathrm{C}$ to $150 ^{\circ}\mathrm{C})$. All units post stress clean passed without any failure. The overall leakage failure rate at ATE test is reduced.