Zhiqiang Lu, Yuze Niu, Zhongjian Chen, Bowei An, Yacong Zhang, Wengao Lu
{"title":"用于$10\\mu\\ mathm {m}$ Pitch $640\\times 512$红外焦平面阵列的低功耗高线性低温读出集成电路","authors":"Zhiqiang Lu, Yuze Niu, Zhongjian Chen, Bowei An, Yacong Zhang, Wengao Lu","doi":"10.1109/ICICM50929.2020.9292261","DOIUrl":null,"url":null,"abstract":"This paper presents a low power cryogenic readout integrated circuit(ROIC) with large charge handling capacity for $640\\times 512$ infrared focal plane array(IRFPA). An innovative structure using two-stage cascaded source followers in output buffer circuit is proposed to reduce the power consumption of the readout integrated circuit and ensure high linearity of the output voltage. Besides, the area of the integration capacitor in pixel array is maintained as large as possible to ensure large charge handling capacity through a special-shape layout structure. The readout integrated circuit implements frame rate of 100Hz, charge handling capacity of 7.28Me−, nonlinearity of 0.87‰ and power consumption of 61mW with $4\\times 10\\text{MHz}$ output rate when the integration mode is integration while reading(IWR).","PeriodicalId":364285,"journal":{"name":"2020 IEEE 5th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2020-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A Low Power High Linearity Cryogenic Readout Integrated Circuit with Large Charge Handling Capacity for $10\\\\mu\\\\mathrm{m}$ Pitch $640\\\\times 512$ Infrared Focal Plane Array\",\"authors\":\"Zhiqiang Lu, Yuze Niu, Zhongjian Chen, Bowei An, Yacong Zhang, Wengao Lu\",\"doi\":\"10.1109/ICICM50929.2020.9292261\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a low power cryogenic readout integrated circuit(ROIC) with large charge handling capacity for $640\\\\times 512$ infrared focal plane array(IRFPA). An innovative structure using two-stage cascaded source followers in output buffer circuit is proposed to reduce the power consumption of the readout integrated circuit and ensure high linearity of the output voltage. Besides, the area of the integration capacitor in pixel array is maintained as large as possible to ensure large charge handling capacity through a special-shape layout structure. The readout integrated circuit implements frame rate of 100Hz, charge handling capacity of 7.28Me−, nonlinearity of 0.87‰ and power consumption of 61mW with $4\\\\times 10\\\\text{MHz}$ output rate when the integration mode is integration while reading(IWR).\",\"PeriodicalId\":364285,\"journal\":{\"name\":\"2020 IEEE 5th International Conference on Integrated Circuits and Microsystems (ICICM)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2020-10-23\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2020 IEEE 5th International Conference on Integrated Circuits and Microsystems (ICICM)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICICM50929.2020.9292261\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 IEEE 5th International Conference on Integrated Circuits and Microsystems (ICICM)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICICM50929.2020.9292261","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A Low Power High Linearity Cryogenic Readout Integrated Circuit with Large Charge Handling Capacity for $10\mu\mathrm{m}$ Pitch $640\times 512$ Infrared Focal Plane Array
This paper presents a low power cryogenic readout integrated circuit(ROIC) with large charge handling capacity for $640\times 512$ infrared focal plane array(IRFPA). An innovative structure using two-stage cascaded source followers in output buffer circuit is proposed to reduce the power consumption of the readout integrated circuit and ensure high linearity of the output voltage. Besides, the area of the integration capacitor in pixel array is maintained as large as possible to ensure large charge handling capacity through a special-shape layout structure. The readout integrated circuit implements frame rate of 100Hz, charge handling capacity of 7.28Me−, nonlinearity of 0.87‰ and power consumption of 61mW with $4\times 10\text{MHz}$ output rate when the integration mode is integration while reading(IWR).