源同步前端总线上I/O时钟抖动的发现和注意事项

2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems Pub Date : 2012-10-01 DOI:10.1109/EPEPS.2012.6457907

D. Dreps, L. Daniels, R. Mandrekar, N. Pham, L. Shan

{"title":"源同步前端总线上I/O时钟抖动的发现和注意事项","authors":"D. Dreps, L. Daniels, R. Mandrekar, N. Pham, L. Shan","doi":"10.1109/EPEPS.2012.6457907","DOIUrl":null,"url":null,"abstract":"This paper outlines when designing a front side bus that is source synchronous the clock needs special consideration. If the clock is treated the same as data bit the bus performance or bit rate can be limited by the clock distortion effects. Investigations of the components of the distortion are described along with prevention rules and silicon architecture impacts.","PeriodicalId":188377,"journal":{"name":"2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems","volume":"25 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Findings and considerations for I/O clock jitter on a source synchronous front side bus\",\"authors\":\"D. Dreps, L. Daniels, R. Mandrekar, N. Pham, L. Shan\",\"doi\":\"10.1109/EPEPS.2012.6457907\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper outlines when designing a front side bus that is source synchronous the clock needs special consideration. If the clock is treated the same as data bit the bus performance or bit rate can be limited by the clock distortion effects. Investigations of the components of the distortion are described along with prevention rules and silicon architecture impacts.\",\"PeriodicalId\":188377,\"journal\":{\"name\":\"2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems\",\"volume\":\"25 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2012-10-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EPEPS.2012.6457907\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EPEPS.2012.6457907","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 0

摘要

本文概述了在设计源同步前端总线时，时钟需要特别考虑的问题。如果将时钟视为数据位，则总线性能或比特率可能受到时钟失真效应的限制。研究了畸变的组成以及防止规则和硅结构的影响。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

Findings and considerations for I/O clock jitter on a source synchronous front side bus

This paper outlines when designing a front side bus that is source synchronous the clock needs special consideration. If the clock is treated the same as data bit the bus performance or bit rate can be limited by the clock distortion effects. Investigations of the components of the distortion are described along with prevention rules and silicon architecture impacts.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems

自引率

0.00%

发文量