提高片上寄生提取的准确性

Electrical Performance of Electronic Packaging Pub Date : 1997-10-27 DOI:10.1109/EPEP.1997.634035

Ching-Chao Huang, K. S. Oh, Shunxi Wang, S. Panchapakesan

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引用次数: 6

摘要

基于规则的布局参数提取(LPE)工具最常用于提取全芯片寄生，但其精度很大程度上取决于如何指定电容模型。本文表明，通过数千场求解器仿真和非线性回归，可以自动生成精确的电容模型。讨论了LPE工具的基本限制。最后，利用三维蒙特卡罗场求解器对LPE结果进行验证和进一步改进。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Improving the accuracy of on-chip parasitic extraction

The rule-based layout parameter extraction (LPE) tools are most often used to extract the full-chip parasitics, but their accuracy strongly depends on how the capacitance models are specified. This paper shows that the generation of accurate capacitance models can be automated with thousands of field-solver simulations and nonlinear regression. The fundamental limitations of LPE tools are discussed. Finally, a 3D Monte-Carlo field solver is used to validate and further improve the LPE results.

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Electrical Performance of Electronic Packaging

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