双N/P-LDMOS晶体管的TCAD优化

2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC) Pub Date : 2011-10-13 DOI:10.1109/ESSDERC.2011.6044188

S. Poli, S. Reggiani, R. K. Sharma, G. Baccarani, E. Gnani, A. Gnudi, M. Denison

{"title":"双N/P-LDMOS晶体管的TCAD优化","authors":"S. Poli, S. Reggiani, R. K. Sharma, G. Baccarani, E. Gnani, A. Gnudi, M. Denison","doi":"10.1109/ESSDERC.2011.6044188","DOIUrl":null,"url":null,"abstract":"The physical behavior of the dual N/P-LDMOS device concept is reviewed and analyzed. Through a proper optimization, a scalable device with good RSP vs. VBD performance in a range of 20–150 V is identified. Further, the current expansion at high gate and drain biases is fully explained by means of TCAD simulations and nicely exploited for the design of an LDO linear voltage regulator with excellent performance in terms of both drop-out voltage and maximum load current.","PeriodicalId":161896,"journal":{"name":"2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"TCAD optimization of a dual N/P-LDMOS transistor\",\"authors\":\"S. Poli, S. Reggiani, R. K. Sharma, G. Baccarani, E. Gnani, A. Gnudi, M. Denison\",\"doi\":\"10.1109/ESSDERC.2011.6044188\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The physical behavior of the dual N/P-LDMOS device concept is reviewed and analyzed. Through a proper optimization, a scalable device with good RSP vs. VBD performance in a range of 20–150 V is identified. Further, the current expansion at high gate and drain biases is fully explained by means of TCAD simulations and nicely exploited for the design of an LDO linear voltage regulator with excellent performance in terms of both drop-out voltage and maximum load current.\",\"PeriodicalId\":161896,\"journal\":{\"name\":\"2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC)\",\"volume\":\"26 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2011-10-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ESSDERC.2011.6044188\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSDERC.2011.6044188","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 4

摘要

回顾和分析了双N/P-LDMOS器件概念的物理行为。通过适当的优化，确定了在20-150 V范围内具有良好RSP与VBD性能的可扩展器件。此外，通过TCAD模拟充分解释了高栅极和漏极偏置下的电流扩展，并很好地利用了LDO线性稳压器的设计，该稳压器在降压和最大负载电流方面都具有优异的性能。

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TCAD optimization of a dual N/P-LDMOS transistor

The physical behavior of the dual N/P-LDMOS device concept is reviewed and analyzed. Through a proper optimization, a scalable device with good RSP vs. VBD performance in a range of 20–150 V is identified. Further, the current expansion at high gate and drain biases is fully explained by means of TCAD simulations and nicely exploited for the design of an LDO linear voltage regulator with excellent performance in terms of both drop-out voltage and maximum load current.

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2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC)

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