{"title":"NAND闪存缩放的最新发展","authors":"K. Parat","doi":"10.1109/VTSA.2009.5159310","DOIUrl":null,"url":null,"abstract":"NAND Flash cell has scaled by ≫l000X in area since its inception over 2 decades ago. There are, however, several scaling challenges that need to be overcome to continue scaling below the 3X node. Many evolutionary and revolutionary approaches, such as high-K inter-poly-dielectric (IPD), engineered tunnel barriers, trap based charge storage devices, as well as 3-D structures are being pursued to overcome these scaling challenges. The paper will discuss some of these challenges and related developments.","PeriodicalId":309622,"journal":{"name":"2009 International Symposium on VLSI Technology, Systems, and Applications","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2009-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Recent developments in NAND flash scaling\",\"authors\":\"K. Parat\",\"doi\":\"10.1109/VTSA.2009.5159310\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"NAND Flash cell has scaled by ≫l000X in area since its inception over 2 decades ago. There are, however, several scaling challenges that need to be overcome to continue scaling below the 3X node. Many evolutionary and revolutionary approaches, such as high-K inter-poly-dielectric (IPD), engineered tunnel barriers, trap based charge storage devices, as well as 3-D structures are being pursued to overcome these scaling challenges. The paper will discuss some of these challenges and related developments.\",\"PeriodicalId\":309622,\"journal\":{\"name\":\"2009 International Symposium on VLSI Technology, Systems, and Applications\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2009-04-27\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2009 International Symposium on VLSI Technology, Systems, and Applications\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VTSA.2009.5159310\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 International Symposium on VLSI Technology, Systems, and Applications","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VTSA.2009.5159310","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
NAND Flash cell has scaled by ≫l000X in area since its inception over 2 decades ago. There are, however, several scaling challenges that need to be overcome to continue scaling below the 3X node. Many evolutionary and revolutionary approaches, such as high-K inter-poly-dielectric (IPD), engineered tunnel barriers, trap based charge storage devices, as well as 3-D structures are being pursued to overcome these scaling challenges. The paper will discuss some of these challenges and related developments.
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