一种用于提取总电离剂量阈值电压位移的晶体管阵列

2022 IEEE International Integrated Reliability Workshop (IIRW) Pub Date : 2022-10-09 DOI:10.1109/IIRW56459.2022.10032746

L. Clark, Clifford Youngsciortino, Maximilian Siath, Leonardo Martinez, W. Brown, Shayena Khandker, Azad Derbedrosian, Sungho Kim, Ryan Melendez, S. Guertin, J. Yang-Scharlotta

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引用次数: 1

摘要

总电离剂量(TID)对完全耗尽绝缘体上硅(FDSOI)晶体管有显著影响，其特征为栅极阈值电压(Vth)偏移。我们提出了晶体管阵列测试结构来测试晶体管TID。由此产生的结构是一个被测器件(DUT)在一个更大的测试集成电路(IC)上。晶体管阵列允许在封装芯片中对大量器件进行TID测试，该封装芯片适用于伽马辐射和其他可靠性研究，采用22 nm FDSOI工艺制造。然而，该方法适用于任何制造过程。

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A Transistor Array for Extracting Total Ionizing Dose Threshold Voltage Shifts

Total ionizing dose (TID) has a significant effect on fully depleted silicon on insulator (FDSOI) transistors, which can be characterized the front gate threshold voltage (Vth) shift. We present transistor array test structure to characterize transistor TID. The resulting structure is one device under test (DUT) on a larger test integrated circuit (IC). The transistor array allows TID testing of a largenumber of devices in a packaged die that is amenable to gamma irradiation and other reliability studies, fabricated on a 22 nm FDSOI process. The approach is however, applicable to any fabrication process.

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2022 IEEE International Integrated Reliability Workshop (IIRW)

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