高速存储总线在背板和布线环境下的链路分析与设计

N. Na, Tao Wang, Scot Baumgartner, R. Mandrekar, Yaping Zhou
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引用次数: 1

摘要

本文通过频域和时域的建模和仿真分析,讨论了各种服务器存储系统配置中SAS (Serial Attached SCSI)链路通道的电气性能和设计方面的问题。研究了两种互连结构下的信号损耗行为,即主机框背板内部SAS链路和布线环境下的外部SAS链路。虽然外部SAS链路中的信号通过以米为单位的长电缆经历了过多的损耗,但内部SAS链路的信号受到电路板组件在不到几英尺的PCB路由上的多个不连续的损害,尽管这在很大程度上取决于系统设计。虽然通常情况下闭眼与损失幅度平行,但通道频率损失行为中表现出的较高程度的不连续导致更多的闭眼,尽管损失幅度较低,减少了设计空间预算,并且随着数据速率的提高,影响更大。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Link analysis and design of high speed storage buses in backplane and cabling environments
This paper discusses electrical performance and design aspects of SAS (Serial Attached SCSI) link channels in various server storage system configurations through modeling and simulation analysis in frequency and time domain. The signal loss behaviors are investigated in two interconnect structures, internal SAS links in host enclosure backplanes and external SAS links in cabling environment. While signals in external SAS links experience excessive loss through lengthy cables in meters, those of internal SAS links are impaired by multiple discontinuities of board components over less than a couple of feet of PCB routing though largely dependent of system design. While eye closure is parallel to loss magnitude in general, higher degree of discontinuities exhibited in frequency loss behavior of channels result in more eye closure despite lower loss magnitude reducing design space budget and the impact is greater with higher data rates.
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