沟道掺杂剂浓度和温度对低压VDMOS晶体管导通电阻的影响

1998 International Semiconductor Conference. CAS'98 Proceedings (Cat. No.98TH8351) Pub Date : 1998-10-06 DOI:10.1109/SMICND.1998.732323

Z. Pavlović, I. Manic, Z. Prijić, N. Stojadinovic

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引用次数: 1

摘要

本文研究了低电压(100 V)功率VDMOS晶体管沟道区最大掺杂浓度和温度对导通电阻的影响。除几何参数外，低压VDMOS器件的导通电阻主要由阈值电压和载流子迁移率值决定。因此，我们的理论考虑涉及掺杂浓度和温度变化对阈值电压和载流子迁移率行为的影响。对通道掺杂浓度范围为10/sup 16/ cm/sup -3/至10/sup 17/ cm/sup -3/的器件进行了理论预测，并与300 K至473 K温度下的实验测量结果进行了比较。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Influence of channel dopant concentration and temperature on low-voltage VDMOS transistor ON-resistance

In this paper effects of the maximum dopant concentration in the channel region and temperature on the ON-resistance in low-voltage (100 V) power VDMOS transistors are investigated. Besides geometrical parameters, the ON-resistance of low-voltage VDMOS devices is mainly determined by the threshold voltage and carrier mobility values. For that reason, our theoretical considerations involve effects of dopant concentration and temperature changes on both the threshold voltage and carrier mobility behavior. Theoretical predictions for devices with channel dopant concentration in the range from 10/sup 16/ cm/sup -3/ to 10/sup 17/ cm/sup -3/ are compared with experimental measurements at temperatures between 300 K and 473 K.

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来源期刊

1998 International Semiconductor Conference. CAS'98 Proceedings (Cat. No.98TH8351)

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