TELE: a timing evaluator using layout estimation for high level applications

The authors address the problem of early accurate timing prediction of VLSI layouts, prior to any physical design tasks. The authors present an approach based on two models, analytical and constructive. This approach permits the user to trade off the accuracy of the prediction versus the runtime of the predictor. Such a scheme is quite useful for high level design tasks such as high-level synthesis and system level partitioning. The authors experimentally validated the model with respect to standard benchmark circuits from MCNC and the results indicate a 13% or better accuracy in the worst case delay predictions for Standard Cell designs with up to 1800 cells.<>