P. Kirsch, R. Hill, J. Huang, W. Loh, T. Kim, M. Wong, B. Min, C. Huffman, D. Veksler, C. Young, K. Ang, I. Ali, R. T. Lee, T. Ngai, A. Wang, W. Wang, T. Cunningham, Y. T. Chen, P. Hung, E. Bersch, B. Sassman, M. Cruz, S. Trammell, R. Droopad, S. Oktybrysky, J. Lee, G. Bersuker, C. Hobbs, R. Jammy
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引用次数: 4
摘要
III-V材料优越的输运特性有望在低功率下实现更好的性能。本文研究了III-V材料在10纳米或以上技术节点的先进CMOS中的模块挑战，并报道了XjD=5×1019 cm-3， ρc= 6Ω的VLSI兼容epi，结，触点和栅极堆栈工艺模块。μm2, Dit = 4×1012 eV-1 cm-2。Si VLSI晶圆厂和ESH协议已经开发，以实现先进的工艺流程。
Challenges of III–V materials in advanced CMOS logic
The superior transport properties of III-V materials are promising candidates to achieve improved performance at low power. This paper examines the module challenges of III-V materials in advanced CMOS at or beyond the 10 nm technology node, and reports VLSI compatible epi, junction, contact and gate stack process modules with Xj<;60;10nm, ND=5×1019 cm-3, ρc= 6Ω.μm2 and Dit = 4×1012 eV-1 cm-2. Si VLSI fab and ESH protocols have been developed to enable advanced process flows.
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