Gb/s CMOS 1-4速率CDR,带频率检测器和偏差校准

S. Tontisirin, R. Tielert
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引用次数: 3

摘要

提出了一种采用1/4速率数字四相关频率检测器和倾斜校准多相压控振荡器的1-2.25 Gb/s时钟和数据恢复(CDR)电路。采用1/4速率时钟架构,无线圈振荡器可以具有较低的工作频率,提供足够的低抖动操作。此外,它是一个固有的1对4的DEMUX。为了减小多相时钟发生器的相位偏移,采用了偏斜校正方案。带频率检测器的CDR环路带宽小,拉入范围宽,无需本地参考时钟即可工作。这种1/4速率CDR采用标准的0.18 μ m CMOS技术实现。它的有效面积为0.7 mm2,在1.8V电源下消耗100mW。话单在1-2.25 Gb/s的宽频率范围内具有低抖动。测量误码率小于10-12 2.25 Gb/s输入数据27-1 PRBS,抖动峰对峰0.7单位间隔(UI)调制在10 MHz
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Gb/s CMOS 1-4th-rate CDR with Frequency Detector and Skew calibration
A 1-2.25 Gb/s clock and data recovery (CDR) circuit using 1/4th-rate digital quadricorrelator frequency detector and skew-calibrated multi-phase voltage-controlled oscillator is presented. With 1/4th-rate clock architecture, the coil-free oscillator can have lower operation frequency providing sufficient low-jitter operation. Moreover, it is an inherent 1-to-4 DEMUX. The skew calibration scheme is applied to reduce phase offset in multi-phase clock generator. The CDR with frequency detector can have small loop bandwidth, wide pull-in range and can operate without the need for a local reference clock. This 1/4th-rate CDR is implemented in standard 0.18mum CMOS technology. It has an active area of 0.7 mm2 and consumes 100mW at 1.8V supply. The CDR has low jitter operation in a wide frequency range from 1-2.25 Gb/s. Measurement of bit-error rate is less than 10-12 for 2.25 Gb/s incoming data 27-1 PRBS, jitter peak-to-peak of 0.7 unit interval(UI) modulation at 10 MHz
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