{"title":"Gb/s CMOS 1-4速率CDR,带频率检测器和偏差校准","authors":"S. Tontisirin, R. Tielert","doi":"10.1109/VDAT.2006.258156","DOIUrl":null,"url":null,"abstract":"A 1-2.25 Gb/s clock and data recovery (CDR) circuit using 1/4th-rate digital quadricorrelator frequency detector and skew-calibrated multi-phase voltage-controlled oscillator is presented. With 1/4th-rate clock architecture, the coil-free oscillator can have lower operation frequency providing sufficient low-jitter operation. Moreover, it is an inherent 1-to-4 DEMUX. The skew calibration scheme is applied to reduce phase offset in multi-phase clock generator. The CDR with frequency detector can have small loop bandwidth, wide pull-in range and can operate without the need for a local reference clock. This 1/4th-rate CDR is implemented in standard 0.18mum CMOS technology. It has an active area of 0.7 mm2 and consumes 100mW at 1.8V supply. The CDR has low jitter operation in a wide frequency range from 1-2.25 Gb/s. Measurement of bit-error rate is less than 10-12 for 2.25 Gb/s incoming data 27-1 PRBS, jitter peak-to-peak of 0.7 unit interval(UI) modulation at 10 MHz","PeriodicalId":356198,"journal":{"name":"2006 International Symposium on VLSI Design, Automation and Test","volume":"95 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Gb/s CMOS 1-4th-rate CDR with Frequency Detector and Skew calibration\",\"authors\":\"S. Tontisirin, R. Tielert\",\"doi\":\"10.1109/VDAT.2006.258156\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 1-2.25 Gb/s clock and data recovery (CDR) circuit using 1/4th-rate digital quadricorrelator frequency detector and skew-calibrated multi-phase voltage-controlled oscillator is presented. With 1/4th-rate clock architecture, the coil-free oscillator can have lower operation frequency providing sufficient low-jitter operation. Moreover, it is an inherent 1-to-4 DEMUX. The skew calibration scheme is applied to reduce phase offset in multi-phase clock generator. The CDR with frequency detector can have small loop bandwidth, wide pull-in range and can operate without the need for a local reference clock. This 1/4th-rate CDR is implemented in standard 0.18mum CMOS technology. It has an active area of 0.7 mm2 and consumes 100mW at 1.8V supply. The CDR has low jitter operation in a wide frequency range from 1-2.25 Gb/s. Measurement of bit-error rate is less than 10-12 for 2.25 Gb/s incoming data 27-1 PRBS, jitter peak-to-peak of 0.7 unit interval(UI) modulation at 10 MHz\",\"PeriodicalId\":356198,\"journal\":{\"name\":\"2006 International Symposium on VLSI Design, Automation and Test\",\"volume\":\"95 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2006-04-26\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2006 International Symposium on VLSI Design, Automation and Test\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VDAT.2006.258156\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 International Symposium on VLSI Design, Automation and Test","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VDAT.2006.258156","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Gb/s CMOS 1-4th-rate CDR with Frequency Detector and Skew calibration
A 1-2.25 Gb/s clock and data recovery (CDR) circuit using 1/4th-rate digital quadricorrelator frequency detector and skew-calibrated multi-phase voltage-controlled oscillator is presented. With 1/4th-rate clock architecture, the coil-free oscillator can have lower operation frequency providing sufficient low-jitter operation. Moreover, it is an inherent 1-to-4 DEMUX. The skew calibration scheme is applied to reduce phase offset in multi-phase clock generator. The CDR with frequency detector can have small loop bandwidth, wide pull-in range and can operate without the need for a local reference clock. This 1/4th-rate CDR is implemented in standard 0.18mum CMOS technology. It has an active area of 0.7 mm2 and consumes 100mW at 1.8V supply. The CDR has low jitter operation in a wide frequency range from 1-2.25 Gb/s. Measurement of bit-error rate is less than 10-12 for 2.25 Gb/s incoming data 27-1 PRBS, jitter peak-to-peak of 0.7 unit interval(UI) modulation at 10 MHz