一种利用DRAM单元阵列检测极低泄漏电流的新型测试装置

ICMTS 93 Proceedings of the 1993 International Conference on Microelectronic Test Structures Pub Date : 1993-03-22 DOI:10.1109/ICMTS.1993.292879

T. Oasa, H. Inada, M. Fujito, T. Matsumoto

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引用次数: 0

摘要

提出了一种测量极低泄漏电流的方法。该方法被称为可变V/sub / pc/方法，能够在8.7*9.4 μ m/sup 2/的范围内检测到低于10/sup -14/ A的泄漏电流。该方法用于测量硅片中氧化层错(OSFs)引起的泄漏电流。定量地评价了osf的泄漏电流。

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A new test device for detecting very low leakage current using DRAM cell array

A method for measuring very low leakage current is presented. The method, named the variable V/sub pc/ method, is capable of detecting leakage current lower than 10/sup -14/ A in the area of 8.7*9.4 mu m/sup 2/ using a dynamic RAM (DRAM) cell. This method is used to measure the leakage current caused by oxidation-induced stacking faults (OSFs) originating in a Si wafer. The leakage current of OSFs is evaluated quantitatively.<>

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ICMTS 93 Proceedings of the 1993 International Conference on Microelectronic Test Structures

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