{"title":"高性能0.35 /spl mu/m 3.3 V BiCMOS技术，优化产品从0.6 /spl mu/m 3.3 V BiCMOS技术移植","authors":"J. Schutz, M. Bohr","doi":"10.1109/BIPOL.1995.493862","DOIUrl":null,"url":null,"abstract":"A 0.35 /spl mu/m logic technology has been developed with high performance transistors and four layers of planarized metal interconnect. A 2.5 V version offers lower power and higher performance. A 3.3 V BiCMOS version has been optimized for compatibility with previous designs implemented in a 0.6 /spl mu/m 3.3 V BiCMOS process. The design process for converting an existing production worthy 0.6 /spl mu/m 3.3 V BiCMOS design is described. The silicon results are described.","PeriodicalId":230944,"journal":{"name":"Proceedings of Bipolar/Bicmos Circuits and Technology Meeting","volume":"24 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"A high performance 0.35 /spl mu/m 3.3 V BiCMOS technology optimized for product porting from a 0.6 /spl mu/m 3.3 V BiCMOS technology\",\"authors\":\"J. Schutz, M. Bohr\",\"doi\":\"10.1109/BIPOL.1995.493862\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 0.35 /spl mu/m logic technology has been developed with high performance transistors and four layers of planarized metal interconnect. A 2.5 V version offers lower power and higher performance. A 3.3 V BiCMOS version has been optimized for compatibility with previous designs implemented in a 0.6 /spl mu/m 3.3 V BiCMOS process. The design process for converting an existing production worthy 0.6 /spl mu/m 3.3 V BiCMOS design is described. The silicon results are described.\",\"PeriodicalId\":230944,\"journal\":{\"name\":\"Proceedings of Bipolar/Bicmos Circuits and Technology Meeting\",\"volume\":\"24 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1995-10-02\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of Bipolar/Bicmos Circuits and Technology Meeting\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/BIPOL.1995.493862\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of Bipolar/Bicmos Circuits and Technology Meeting","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/BIPOL.1995.493862","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
摘要
采用高性能晶体管和四层平面化金属互连技术，开发了一种0.35 /spl mu/m的逻辑技术。2.5 V版本提供更低的功耗和更高的性能。3.3 V BiCMOS版本已经过优化，可与以前在0.6 /spl mu/m 3.3 V BiCMOS工艺中实现的设计兼容。介绍了现有生产价值0.6 /spl mu/m 3.3 V BiCMOS设计的改造设计过程。描述了硅的结果。
A high performance 0.35 /spl mu/m 3.3 V BiCMOS technology optimized for product porting from a 0.6 /spl mu/m 3.3 V BiCMOS technology
A 0.35 /spl mu/m logic technology has been developed with high performance transistors and four layers of planarized metal interconnect. A 2.5 V version offers lower power and higher performance. A 3.3 V BiCMOS version has been optimized for compatibility with previous designs implemented in a 0.6 /spl mu/m 3.3 V BiCMOS process. The design process for converting an existing production worthy 0.6 /spl mu/m 3.3 V BiCMOS design is described. The silicon results are described.
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