Impact of system level thermal solution on the interconnect reliability of high performance and high heat dissipating CSP package

A custom SRAM was developed for high performance and high reliability network switching applications using 90 nm low-k silicon technology. It is a 13.6 mm x 18.4 mm flip chip chip scale package (CSP) with a 11.12 mm x 16.36 mm die. The package has 838 BGA balls at 0.5 mm pitch. The 0.5 mm ball pitch CSP minimizes electrical package parasitics and enables higher data rate performance. However, the high aspect ratio of the die-to-package area leaves very little room for underfill dispensing and no room for a stiffener ring attachment. In addition, the high heat dissipation of the device requires the use of a metal heatspreader flip chip package as opposed to an overmolded flip chip package solution. The package design coupled with a large die and high I/O count presents significant challenges in the package assembly process and interconnect reliability. A lower glass transition (Tg) underfill material is typically preferred to reduce package warpage and to reduce the stress in the low-k dielectric caused by CTE mismatch between the silicon die and package materials. However, for high power applications where the operating temperature is very close to the underfill Tg, the system level thermal solution must be optimized for improved cooling while at the same time ensuring that the interconnect and package reliability at the system application level is not compromised. In this paper, both Experimental and Finite Element analyses were performed to investigate the key system level thermal solution design parameters that impact package interconnect reliability. The effect of heatsink compressive loading on the thermal excursions, the underfill material, and the interconnect metallurgy was evaluated. In addition to the compressive loading effect, the effect of the heatsink attachment method on interconnect reliability was also investigated. Three dimensional fatigue analyses were performed to derive the hysteresis loops for different test cases, to understand the interaction between the heatsink attachment method and the package material and design variables. The finite element model data was benchmarked against experimental data to determine the optimal design conditions for effective thermal cooling without compromising interconnect reliability. Real time pressure measurement and failure analysis were also performed to understand the potential failure modes and failure rates occurring in the system level design. Finally, recommendations are provided on ways to mitigate critical failure modes in the thermal and interconnect design of such complex flip chip CSP packages at the system level.