L. Ragnarsson, T. Schram, E. Rohr, F. Sebaai, P. Kelkar, M. Wada, T. Kauerauf, M. Aoulaiche, M. Cho, S. Kubicek, A. Lauwers, T. Hoffmann, P. Absil, S. Biesemans
{"title":"单金属双介电(SMDD)栅极优先CMOS集成，实现低VT和高性能","authors":"L. Ragnarsson, T. Schram, E. Rohr, F. Sebaai, P. Kelkar, M. Wada, T. Kauerauf, M. Aoulaiche, M. Cho, S. Kubicek, A. Lauwers, T. Hoffmann, P. Absil, S. Biesemans","doi":"10.1109/VTSA.2009.5159287","DOIUrl":null,"url":null,"abstract":"This paper overviews integration challenges of low-V<inf>T</inf> gate-first CMOS featuring one metal gate electrode and one host dielectric with Al<inf>2</inf>O<inf>3</inf> and La<inf>2</inf>O<inf>3</inf> cap-dielectrics for pMOS and nMOS respectively. The advantages and disadvantages of employed low EOT low V<inf>T</inf> enabling technologies are compared with respect to processing simplicity as well as device performance and reliability. The latest state-of-the art SMDD device results are reported.","PeriodicalId":309622,"journal":{"name":"2009 International Symposium on VLSI Technology, Systems, and Applications","volume":"10 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Single-Metal Dual-Dielectric (SMDD) gate-first CMOS integration towards low VT and high performance\",\"authors\":\"L. Ragnarsson, T. Schram, E. Rohr, F. Sebaai, P. Kelkar, M. Wada, T. Kauerauf, M. Aoulaiche, M. Cho, S. Kubicek, A. Lauwers, T. Hoffmann, P. Absil, S. Biesemans\",\"doi\":\"10.1109/VTSA.2009.5159287\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper overviews integration challenges of low-V<inf>T</inf> gate-first CMOS featuring one metal gate electrode and one host dielectric with Al<inf>2</inf>O<inf>3</inf> and La<inf>2</inf>O<inf>3</inf> cap-dielectrics for pMOS and nMOS respectively. The advantages and disadvantages of employed low EOT low V<inf>T</inf> enabling technologies are compared with respect to processing simplicity as well as device performance and reliability. The latest state-of-the art SMDD device results are reported.\",\"PeriodicalId\":309622,\"journal\":{\"name\":\"2009 International Symposium on VLSI Technology, Systems, and Applications\",\"volume\":\"10 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2009-04-27\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2009 International Symposium on VLSI Technology, Systems, and Applications\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VTSA.2009.5159287\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 International Symposium on VLSI Technology, Systems, and Applications","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VTSA.2009.5159287","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Single-Metal Dual-Dielectric (SMDD) gate-first CMOS integration towards low VT and high performance
This paper overviews integration challenges of low-VT gate-first CMOS featuring one metal gate electrode and one host dielectric with Al2O3 and La2O3 cap-dielectrics for pMOS and nMOS respectively. The advantages and disadvantages of employed low EOT low VT enabling technologies are compared with respect to processing simplicity as well as device performance and reliability. The latest state-of-the art SMDD device results are reported.
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