用于64mbit 16级单元非易失性存储器的混合传感结构

1996 Proceedings. Eighth Annual IEEE International Conference on Innovative Systems in Silicon Pub Date : 1996-10-09 DOI:10.1109/ICISS.1996.552420

C. Calligaro, A. Manstretta, P. Rolandi, G. Torelli

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引用次数: 5

摘要

提出了一种多电平非易失性存储器的传感结构。传感是按照二分类算法进行的，其中每个搜索步骤执行许多并行比较。当每个单元使用三个感测放大器时，两个感测步骤能够检测多达16个电平(4位)。该架构适用于16mcell (64mbit) eprom，其中存储单元经过工厂编程，以保证可靠存储和检测所需的严格阈值电压分布。

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Mixed sensing architecture for 64 Mbit 16-level-cell nonvolatile memories

This paper presents a sensing architecture for multilevel non-volatile memories. Sensing is carried out following a dichotomic algorithm, where each search step performs a number of parallel comparisons. Two sensing steps are able to detect as many as 16 levels (4 bits) when using three sense amplifiers per cell to be detected. The architecture is suitable for 16 Mcells (64 Mbit) EPROMs, where the memory cells are factory programmed to guarantee the tight threshold voltage distribution required for reliable store and sense.

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来源期刊

1996 Proceedings. Eighth Annual IEEE International Conference on Innovative Systems in Silicon

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