New Design Optimized and IC Area Efficient Rules for the Prevention of Plasma Processing Induced Damage on CMOS Circuit Reliability

Plasma processing induced charging damage of MOS transistors is a well-known reliability risk and can be a decrement to product yield or reliability lifetimes, which should be prevented by the implementation of design rules. Simple rules had their origin in the 90’s and since then were copied from process node to process node. They imply some substantial limitations for large and complex ICs on state of the art technology platforms, in particular for advanced well concepts or deep trenches, which introduce insulated areas on an IC. It requires a new rule concept for protective devices when a metal area, which is connected to a MOS transistor gate, exceeds a certain limit. It is shown here for MOS transistors on bulk-silicon with SiO2 and high-K dielectrics that with a new method the size of protective devices can be reduced and a chip designer gains more freedom in the layout process. Especially for complex and large IC’s this new rule concept will improve design robustness against plasma charging.