{"title":"功率模拟电路中的暂态锁存","authors":"V. Vashchenko, D. LaFonteese, A. Concannon","doi":"10.1109/IRPS.2011.5784508","DOIUrl":null,"url":null,"abstract":"Two cases of transient latchup specific to power management analog integrated circuit design are described and analyzed experimentally. The representative case studies include the interaction of a power array and ESD clamp and the interaction of two high voltage ESD clamps","PeriodicalId":242672,"journal":{"name":"2011 International Reliability Physics Symposium","volume":"9 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Transient latchup in power analog circuits\",\"authors\":\"V. Vashchenko, D. LaFonteese, A. Concannon\",\"doi\":\"10.1109/IRPS.2011.5784508\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Two cases of transient latchup specific to power management analog integrated circuit design are described and analyzed experimentally. The representative case studies include the interaction of a power array and ESD clamp and the interaction of two high voltage ESD clamps\",\"PeriodicalId\":242672,\"journal\":{\"name\":\"2011 International Reliability Physics Symposium\",\"volume\":\"9 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2011-04-10\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2011 International Reliability Physics Symposium\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IRPS.2011.5784508\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 International Reliability Physics Symposium","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IRPS.2011.5784508","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Two cases of transient latchup specific to power management analog integrated circuit design are described and analyzed experimentally. The representative case studies include the interaction of a power array and ESD clamp and the interaction of two high voltage ESD clamps
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