ESD设计窗口缩窄至7nm工艺节点的综合研究

2018 40th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD) Pub Date : 2018-09-01 DOI:10.23919/EOS/ESD.2018.8509689

Aihua Dong, J. Xiong, S. Mitra, Wei Liang, R. Gauthier, A. Loiseau

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引用次数: 15

摘要

在350nm7nm节点上，首次比较了主流块体和SOI平面/FinFET技术的ESD设计窗口。介绍并讨论了Vgox的100ns TLP和1ns vftp特性，以及各种逻辑和I/O fet的Vt1和It2特性。讨论了在I/O驱动中利用串联电阻来扩展设计窗口。

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Comprehensive Study of ESD Design Window Scaling Down to 7nm Technology Node

ESD design window for mainstream bulk and SOI planar/FinFET technologies across 350nm7nm node are compared for the first time. 100ns TLP and 1ns vfTLP characteristics of Vgox, and Vt1, and It2 of various logic and I/O FETs are presented anddiscussed. Expanding the design window by utilizing series resistance within I/O driversis discussed.

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2018 40th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)

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