适用于0.15 /spl mu/m CMOS器件的NH/sub /快速热退火W/多晶硅栅极反应势垒形成

Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407) Pub Date : 2000-06-05 DOI:10.1109/IITC.2000.854284

Chang-Hee Han, D. Sohn, Ji-Soo Park, J. Bae, J. Lee, Min-Soo Park, J. Oh, J. Park

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引用次数: 0

摘要

我们发现，在750/spl°C以上对Wi/多晶硅栅极进行NH/sub / 3/快速热退火，可以同时形成高度可靠的原位势垒层和低电阻率W。该阻挡层使Wi/多晶硅栅极在1000/spl℃的高温下保持稳定。经氨处理的W/多晶硅栅极在900/spl度/C下退火30分钟后，其片电阻分布窄，线宽为0.15 /spl mu/m。该W/多晶硅栅极适用于0.15 /spl mu/m的CMOS器件，无需沉积阻挡层。

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Reaction barrier formation of W/poly-Si gate by NH/sub 3/ rapid thermal annealing applicable to 0.15 /spl mu/m CMOS devices

We found that an NH/sub 3/ rapid thermal annealing of Wi/poly-Si gate above 750/spl deg/C resulted in the formation of a highly reliable in-situ barrier layer and low resistivity W, simultaneously. This barrier layer kept the Wi/poly-Si gate stable up to the elevated temperature of 1000/spl deg/C. Ammonia treated W/poly-Si gate showed a narrow distribution of sheet resistance at a line width of 0.15 /spl mu/m after the post annealing at 900/spl deg/C for 30 min. This W/poly-Si gate was acceptable to apply to 0.15 /spl mu/m CMOS devices without deposition of a barrier layer.

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Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407)

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