A Fully Printable, Self-aligned And Planarized Stacked Capacitor DRAM Cell Technology For 1Gbit DRAM And Beyond

Introduction In order to achieve <400mm2 chip size for lGDRAM production, 0.3um pitch fine patterning must be needed. Lithographic printability will be one of serious problems in this generation. In COB type DRAM cell, active area pattem is a kind of problem for both of bitline (BL) and storage node (SN) connections. Simple mask pattem is first key to get a large exposure defocus window. Cell size is represented as a proportion to minimum feature size (F) square. Several studies about 13F2 cell size have been reported for 0.4um pitch devices [ 1,2,3]. Based on historical trends, -8F2 technology will be needed in 0.3um pitch generation. SN contact self-aligned to BL is also second key to realize 8F2 cell. It has been pointed out that wafer planarity throughout the process is third key to achieve a large process window [4]. Especially, this issue is more severe in COB cell. In this paper, relaxed 0.44um pitch memory cell array is demonstrated and three key technologies are adopted such as self-aligned poly plug technology using printable mask pattem, cross point contact technology for SN contact selfaligned to BL, and plariarized concave capacitor technology. Self-aligned Poly Plug Figures 1 and 2 show schematic top view and cross sections to explain self-aligned poly plug technology, respectively. Following simple pattemed active area formation using nomial STI process, straight gate was pattemed, which was (composed of WSi polycide with SiN hard mask. Barrier Sip? and reflowed BPSG interlayer were deposited. BPSG was planarized using CMP stopped by barrier SiN (Fig.2a). SAC was opened by BPSG etching selectively to SIN using Gate SAC mask shown in Fig.1. Gate SAC pattem is t h e same as active area and is shifted by a half pitch to gate direction. Cross sectional SEM photograph after SAC opening is shown in Fig.3. Phosphorous-doped polysilicon was deposited and planarized down to Gate SiN by CMP (Fig.2b), resulting in dense poly plugs self-aligned to gate. Poly plug top view SEM photograph is shown in Fig. 4. Cross Point Contact BL and SN contact formation are explained with Fig.5. After interlayer deposition, straight BL was pattemed and spacer SIN was formed on side walls. BL wiring was fabricated using damaxene tungsten (FigSa). Then, tungsten was etched back and capped with SIN hard mask (FigSb). SiN capping was performed by SiN CMP etching selectively to SiOz. Interlayer was etched selectively to cap SiN using straight SN contact mask perpendicular to BL. Therefore, SN contact was opened at cross point of two levels. Cross point contact with cross sectional SEM photograph is shown in Fig.6. After contact SiN liners were formed as contact inner walls (Fig.%), phosphorous-doped polysilicon was deposited and planarized down to cap SiN by CMP (FigSd). Etched back tungsten sheet resistance distribution is acceptable for BL as shown in Fig.7. Concave Capacitor Figure 8 shows process steps forming planarized concave capacitor, After interlayer deposition, SN hole was opened using 80 degree tapered etching which was stopped by thin SIN layer (Fig.8a). Ruthenium (Ru) as a SN electrode was sputtered with 2Onm thick at tapered side walls and remained in inner hole by CMP etching down to top surface of interlayer (Fig.8b). Then, BST and Ru as a plate electrode were sputtered and the plate was pattemed (Fig&). According to this technology, no step height difference between memory cell and periphery circuit can be achieved to enlarge a process margin for AI wiring. Concave capacitor cross sectional SEM photograph is shown in Fig.9. Sputtered BST dielectric characteristics were investigated in plane capacitors. Ru was used for both of top and bottom electrodes. Following 40nm BST sputtering at 400°C due to avoid bottom electrode oxidation, the film was recrystallized by 750'c RTA. Oxide equivalent thickness of 0.56nm was obtained. The breakdown voltage histogram in whole 6 inch wafer is acceptable for integration as shown in Fig. 10. Scalability of this technology is calculated in Table 1. It is assumed projected SN size of 3FX4/3F with comer rounding, lGnm thick SN electrode on side, uniform deposited films, 260 dielectric constant, and cell capacitance of 2 5 s . Calculation is adjusted for gap with <3 aspect ratio to be filled with plate electrode. BST targets of lGDRAM are 2Onm actual thickness and 0.3nm oxide equivalent thickness. Concave capacitor is scalable to 0.3um pitch generation and beyond. Summary and Conclusions Three key technologies to achieve l G D W production with a wide process window are demonstrated using relaxed memory cell array. All mask pattem are simplified from a standpoint of lithographic printability. SN contact selfaligned to BL is realized by a cross point contact technology. Wafer planarity is kept throughout COB DRAM process using concave capacitor technology. BST targets for 0.3um pitch generation are clarified, such as, 20nm actual thickness, 0.3nm oxide equivalent thickness, uniform deposition, and gap filling process with electrode. Acknowledgments The authors would like to thank K.Maeguchi, T.Takigawa and T.Arikado for their continuous encouragement. The authors also would like to express their appreciation to EShiobara, H.Nomura, H.Ichinose, T.Matsushita, M.Kamikokuryo and H.Kawaguchiya for their support in device fabrication and characterization.