Jin Won Koh, G. Hwang, M. Hyun, Jun-Mo Yang, Jeoung Woo Kim
{"title":"SEM半导体层萃取技术","authors":"Jin Won Koh, G. Hwang, M. Hyun, Jun-Mo Yang, Jeoung Woo Kim","doi":"10.1109/IPFA.2011.5992731","DOIUrl":null,"url":null,"abstract":"Because of a limitation of optical microscope resolution, it is difficult to extract layers of semiconductor devices with a gate size smaller than 180 nm. In this study, we have developed sample preparation methods and image stitching processes for layer extraction by an SEM. This technical development makes it possible to analyze layer information for numerous system ICs.","PeriodicalId":312315,"journal":{"name":"18th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"92 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"Semiconductor layer extraction techniques by SEM\",\"authors\":\"Jin Won Koh, G. Hwang, M. Hyun, Jun-Mo Yang, Jeoung Woo Kim\",\"doi\":\"10.1109/IPFA.2011.5992731\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Because of a limitation of optical microscope resolution, it is difficult to extract layers of semiconductor devices with a gate size smaller than 180 nm. In this study, we have developed sample preparation methods and image stitching processes for layer extraction by an SEM. This technical development makes it possible to analyze layer information for numerous system ICs.\",\"PeriodicalId\":312315,\"journal\":{\"name\":\"18th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)\",\"volume\":\"92 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2011-07-04\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"18th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IPFA.2011.5992731\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"18th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IPFA.2011.5992731","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Because of a limitation of optical microscope resolution, it is difficult to extract layers of semiconductor devices with a gate size smaller than 180 nm. In this study, we have developed sample preparation methods and image stitching processes for layer extraction by an SEM. This technical development makes it possible to analyze layer information for numerous system ICs.