垂直Si n隧道场效应管的电学结果

2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC) Pub Date : 2011-10-13 DOI:10.1109/ESSDERC.2011.6044186

A. Vandooren, D. Leonelli, R. Rooyackers, K. Arstila, G. Groeseneken, C. Huyghebaert

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引用次数: 5

摘要

本文报道了垂直隧道场效应管(tfet)的工艺集成，分析了工艺参数和几何参数对器件性能的影响。门源重叠被证明是一个关键参数，特别是当重叠是边缘时。研究还表明，高界面陷阱密度是垂直ttfet起始特性差的根源，并且改进垂直纳米线表面钝化是有益的。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Electrical results of vertical Si N-Tunnel FETs

This paper reports on the process integration of vertical Tunnel FETs (TFETs) and analyzes the impact of process and geometrical parameters on the device performance. The gate-source overlap is shown to be a critical parameter, especially when the overlap is marginal. The study also suggests that a high interface trap density is at the origin of the poor onset characteristic of the vertical TFET and that improvement in passivating the surface of the vertical nanowires should be beneficial.

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2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC)

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