一个2GSps的12位DAC, SFDR >57.5dBc，最高可达奈奎斯特带宽

2013 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM) Pub Date : 2013-09-01 DOI:10.1109/BCTM.2013.6798180

Lei Zhou, Danyu Wu, Fan Jiang, Jin Wu, Zhi Jin, Xinyu Liu

{"title":"一个2GSps的12位DAC, SFDR >57.5dBc，最高可达奈奎斯特带宽","authors":"Lei Zhou, Danyu Wu, Fan Jiang, Jin Wu, Zhi Jin, Xinyu Liu","doi":"10.1109/BCTM.2013.6798180","DOIUrl":null,"url":null,"abstract":"In this paper we present a 2GSps 12bit current steering digital-to-analog converter (DAC), in 100G Ft 0.18μm SiGe HBT technology. An improved switching sequence is proposed to compensate the gradient error and reduce the impact of cell-dependent-delay-variation. According to measured results, the test chip achieved a DNL/INL of 0.6/0.95 LSB respectively. The measured SFDR at low frequency is above 72dBc, and the lowest SFDR up to Nyquist frequency is above 57.5dBc.","PeriodicalId":272941,"journal":{"name":"2013 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"A 2GSps 12bit DAC with SFDR >57.5dBc up to Nyquist bandwidth\",\"authors\":\"Lei Zhou, Danyu Wu, Fan Jiang, Jin Wu, Zhi Jin, Xinyu Liu\",\"doi\":\"10.1109/BCTM.2013.6798180\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper we present a 2GSps 12bit current steering digital-to-analog converter (DAC), in 100G Ft 0.18μm SiGe HBT technology. An improved switching sequence is proposed to compensate the gradient error and reduce the impact of cell-dependent-delay-variation. According to measured results, the test chip achieved a DNL/INL of 0.6/0.95 LSB respectively. The measured SFDR at low frequency is above 72dBc, and the lowest SFDR up to Nyquist frequency is above 57.5dBc.\",\"PeriodicalId\":272941,\"journal\":{\"name\":\"2013 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM)\",\"volume\":\"47 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2013-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2013 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/BCTM.2013.6798180\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/BCTM.2013.6798180","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 4

摘要

在本文中，我们提出了一个2GSps的12位电流转向数模转换器(DAC)，采用100G Ft 0.18μm SiGe HBT技术。提出了一种改进的切换序列，以补偿梯度误差并减小细胞依赖延迟变化的影响。根据测量结果，测试芯片的DNL/INL分别为0.6/0.95 LSB。低频时测得的SFDR在72dBc以上，奈奎斯特频率以下的最低SFDR在57.5dBc以上。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A 2GSps 12bit DAC with SFDR >57.5dBc up to Nyquist bandwidth

In this paper we present a 2GSps 12bit current steering digital-to-analog converter (DAC), in 100G Ft 0.18μm SiGe HBT technology. An improved switching sequence is proposed to compensate the gradient error and reduce the impact of cell-dependent-delay-variation. According to measured results, the test chip achieved a DNL/INL of 0.6/0.95 LSB respectively. The measured SFDR at low frequency is above 72dBc, and the lowest SFDR up to Nyquist frequency is above 57.5dBc.

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2013 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM)

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