{"title":"优化多层互连结构的溅射薄膜的形成和表征","authors":"W. Sashida, Y. Kimura","doi":"10.1109/EMAP.2005.1598257","DOIUrl":null,"url":null,"abstract":"UBM (under barrier metal) mounted in multilayered interconnection structure is thin film using to prevent counter diffusion between semiconductor substrate and metal line, in connection with multilayered and minute structure, thickness of UBM becomes an issue. Evaluation of UBM with the use of TEG (test element grid) chip was conducted. TEG chip is a unit device that decollates elemental structure of circuit from LSI. With the use of TEG chip, various evaluations concerning LSI structure can be easily conducted. For these reasons, the purposes of this research are to design and to manufacture TEG chip, which have relatively simple multilayered interconnection structure, and also, examinations of optimal material such as Ti-W and morphology of UBM for obtaining superior electro-migration resistance were conducted.","PeriodicalId":352550,"journal":{"name":"2005 International Symposium on Electronics Materials and Packaging","volume":"15 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2005-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Formation and characterization of sputtered thin film for optimizing multilayered interconnection structure\",\"authors\":\"W. Sashida, Y. Kimura\",\"doi\":\"10.1109/EMAP.2005.1598257\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"UBM (under barrier metal) mounted in multilayered interconnection structure is thin film using to prevent counter diffusion between semiconductor substrate and metal line, in connection with multilayered and minute structure, thickness of UBM becomes an issue. Evaluation of UBM with the use of TEG (test element grid) chip was conducted. TEG chip is a unit device that decollates elemental structure of circuit from LSI. With the use of TEG chip, various evaluations concerning LSI structure can be easily conducted. For these reasons, the purposes of this research are to design and to manufacture TEG chip, which have relatively simple multilayered interconnection structure, and also, examinations of optimal material such as Ti-W and morphology of UBM for obtaining superior electro-migration resistance were conducted.\",\"PeriodicalId\":352550,\"journal\":{\"name\":\"2005 International Symposium on Electronics Materials and Packaging\",\"volume\":\"15 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2005-12-11\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2005 International Symposium on Electronics Materials and Packaging\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EMAP.2005.1598257\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2005 International Symposium on Electronics Materials and Packaging","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EMAP.2005.1598257","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
摘要
安装在多层互连结构中的屏障金属(UBM)是一种用于防止半导体衬底与金属线之间反扩散的薄膜，在多层和微细结构中，屏障金属的厚度成为一个问题。利用TEG (test element grid)芯片对UBM进行了评价。TEG芯片是一种从大规模集成电路中提取电路基本结构的单元器件。使用TEG芯片，可以方便地进行有关LSI结构的各种评估。因此，本研究的目的是设计和制造具有相对简单的多层互连结构的TEG芯片，并对Ti-W等最佳材料和UBM的形貌进行了测试，以获得优异的电迁移电阻。
Formation and characterization of sputtered thin film for optimizing multilayered interconnection structure
UBM (under barrier metal) mounted in multilayered interconnection structure is thin film using to prevent counter diffusion between semiconductor substrate and metal line, in connection with multilayered and minute structure, thickness of UBM becomes an issue. Evaluation of UBM with the use of TEG (test element grid) chip was conducted. TEG chip is a unit device that decollates elemental structure of circuit from LSI. With the use of TEG chip, various evaluations concerning LSI structure can be easily conducted. For these reasons, the purposes of this research are to design and to manufacture TEG chip, which have relatively simple multilayered interconnection structure, and also, examinations of optimal material such as Ti-W and morphology of UBM for obtaining superior electro-migration resistance were conducted.
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