Wong Shaw Fong, L. W. Keat, Lee Yung Hsiang, Yap Eng Hooi, Wong Siang Woen, Hin Tze Yang, M. We
{"title":"倒装芯片球栅阵列(FCBGA)在外围元件互连(PCI)板上应用的动态特性研究","authors":"Wong Shaw Fong, L. W. Keat, Lee Yung Hsiang, Yap Eng Hooi, Wong Siang Woen, Hin Tze Yang, M. We","doi":"10.1109/EMAP.2005.1598243","DOIUrl":null,"url":null,"abstract":"This paper outlines and discusses the new mechanical characterization metrologies applied on PCI board envelope. 'The dynamic responses of PCI board were monitored and characterized using accelerometer and strain gauges. PCI board performances were analyzed to differentiate its high risk areas through analysis of board strain responses to solder joint crack. Board \"strain states\" analysis methodology was introduced to provide immediate accurate board bending modes and deflection associated with experimental results. Using this methodology, it eases the board bend mode analysis which can capture the board strain performance limit at the same time. In addition, high speed camera (HSC) tool was incorporated into the evaluation to understand the boards bend history under shock test. This allows better view of the bending moment and matching to defect locations for corrective action implementation. Detailed failure analysis mapping of solder joint crack percentages was successfully gathered to support those findings. Key influences, such as thermal/mechanical enabling preload masses and shock input profiles on solder joint crack severity were conducted as well to understand the potential risk modulators for SJR performance. Furthermore, commercial simulation software analysis tool was applied to correlate the board's bend modes and predict the high risk solder joint location; which is important for product enabling solutions design. As a result, a system level stiffener solution was designed. Hence, with this characterization and validation concept, a practical stiffener solution for PCI application was validated through a special case study to improve the board SJR performance in its use condition.","PeriodicalId":352550,"journal":{"name":"2005 International Symposium on Electronics Materials and Packaging","volume":"35 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2005-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Dynamic characterization study of flip chip ball grid array (FCBGA) on peripheral component interconnect (PCI) board application\",\"authors\":\"Wong Shaw Fong, L. W. Keat, Lee Yung Hsiang, Yap Eng Hooi, Wong Siang Woen, Hin Tze Yang, M. We\",\"doi\":\"10.1109/EMAP.2005.1598243\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper outlines and discusses the new mechanical characterization metrologies applied on PCI board envelope. 'The dynamic responses of PCI board were monitored and characterized using accelerometer and strain gauges. PCI board performances were analyzed to differentiate its high risk areas through analysis of board strain responses to solder joint crack. Board \\\"strain states\\\" analysis methodology was introduced to provide immediate accurate board bending modes and deflection associated with experimental results. Using this methodology, it eases the board bend mode analysis which can capture the board strain performance limit at the same time. In addition, high speed camera (HSC) tool was incorporated into the evaluation to understand the boards bend history under shock test. This allows better view of the bending moment and matching to defect locations for corrective action implementation. Detailed failure analysis mapping of solder joint crack percentages was successfully gathered to support those findings. Key influences, such as thermal/mechanical enabling preload masses and shock input profiles on solder joint crack severity were conducted as well to understand the potential risk modulators for SJR performance. Furthermore, commercial simulation software analysis tool was applied to correlate the board's bend modes and predict the high risk solder joint location; which is important for product enabling solutions design. As a result, a system level stiffener solution was designed. Hence, with this characterization and validation concept, a practical stiffener solution for PCI application was validated through a special case study to improve the board SJR performance in its use condition.\",\"PeriodicalId\":352550,\"journal\":{\"name\":\"2005 International Symposium on Electronics Materials and Packaging\",\"volume\":\"35 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2005-12-11\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2005 International Symposium on Electronics Materials and Packaging\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EMAP.2005.1598243\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2005 International Symposium on Electronics Materials and Packaging","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EMAP.2005.1598243","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Dynamic characterization study of flip chip ball grid array (FCBGA) on peripheral component interconnect (PCI) board application
This paper outlines and discusses the new mechanical characterization metrologies applied on PCI board envelope. 'The dynamic responses of PCI board were monitored and characterized using accelerometer and strain gauges. PCI board performances were analyzed to differentiate its high risk areas through analysis of board strain responses to solder joint crack. Board "strain states" analysis methodology was introduced to provide immediate accurate board bending modes and deflection associated with experimental results. Using this methodology, it eases the board bend mode analysis which can capture the board strain performance limit at the same time. In addition, high speed camera (HSC) tool was incorporated into the evaluation to understand the boards bend history under shock test. This allows better view of the bending moment and matching to defect locations for corrective action implementation. Detailed failure analysis mapping of solder joint crack percentages was successfully gathered to support those findings. Key influences, such as thermal/mechanical enabling preload masses and shock input profiles on solder joint crack severity were conducted as well to understand the potential risk modulators for SJR performance. Furthermore, commercial simulation software analysis tool was applied to correlate the board's bend modes and predict the high risk solder joint location; which is important for product enabling solutions design. As a result, a system level stiffener solution was designed. Hence, with this characterization and validation concept, a practical stiffener solution for PCI application was validated through a special case study to improve the board SJR performance in its use condition.