0.18 /spl mu/m栅极工艺的lna可靠性试验

[Reliability of Compound Semiconductors] ROCS Workshop, 2005. Pub Date : 1900-01-01 DOI:10.1109/ROCS.2005.201563

H. Jen, P. Ersland, C. Gil, Shiou Lung, G. Chu

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引用次数: 0

摘要

使用短栅极长度(0。18um) phemt工艺可以在高频下实现非常低的噪声系数。这一过程的目标是各种商业和军事应用。工艺可靠性测试包括ESD、DPA、HTOL、HAST和TC，测试车辆采用该工艺的500pm栅极外设。本文给出了这些测试的结果。在早期的工程晶圆测试中(来自不同批次)，具有规格PCM数据的晶圆通过了HTOL，平均故障时间为1.42 × 106小时，活化能为1.08eV。可靠性测试结果与用于决定是否接受或拒绝晶圆片的过程控制监视器(PCM)数据非常相关。

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Reliability testing of an lna with 0.18 /spl mu/m gate process

Devices manufactured using a short gate length (0. 18um) pHEMTprocess can achieve very low noisefigure at highfreqzency. This process is targetedfor a variety ofcommercial and military applications. Process reliability tests including ESD, DPA, HTOL, HAST, and TC were performed on a test vehicle with 500pm gate peripheryfrom this process. Results are presentedfor each ofthese tests. Of the early engineering wafers tested (from separate lots), the wafer with in specification PCM data passed HTOL with Mean-Time-To-Failure of 1.42x106 hours and an activation energy of 1.08eV. Reliability test results correlated very well with the process control monitor (PCM) data used to determine whether to accept or reject wafers.

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[Reliability of Compound Semiconductors] ROCS Workshop, 2005.

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