0.25/spl mu/m W-polycide Dual Gate And Buried Metal On Diffusion Layer (BMD) Technology For DRAM-embedded Logic Devices

A 0.25pm logic process technology, which is suitable for high-speed, low-voltage operation, logic and DRAM integration in one chip, has been developed. For fabrication of an embedded DRAM, a high-thermal-stability W-polycide dual gate process was realized using intentional chemical oxide formation for large-grain poly-Si growth. Lateral dopant diffusion and boron penetration through a 5-nm-thick gate oxide are prevented with being annealed at 1000°C for 10 s and then 850°C for 30 min. Furthermore, we have utilized a buried metal on diffusion layer (BMD) structure, and the parasitic resistance has been equal to that of a TiSi, structure.