用激光扫描和电压对比技术研究CMOS锁存

24th International Reliability Physics Symposium Pub Date : 1986-04-01 DOI:10.1109/IRPS.1986.362120

K. S. Wills, C. Pilch, A. Hyslop

{"title":"用激光扫描和电压对比技术研究CMOS锁存","authors":"K. S. Wills, C. Pilch, A. Hyslop","doi":"10.1109/IRPS.1986.362120","DOIUrl":null,"url":null,"abstract":"The susceptibility of CMOS devices to latch-up becomes of greater concern as the spacing between geometries is reduced. An advanced 1 micron CMOS device is used to examine various methods of determining where on the device latch-up might occur. Two of these methods are laser induced latch-up and scanning electron microscope (SEM) microprobe. A correlation is shown between the two methods.","PeriodicalId":354436,"journal":{"name":"24th International Reliability Physics Symposium","volume":"4 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1986-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"A Study of CMOS Latch-up by Laser Scanning and Voltage Contrast Techniques\",\"authors\":\"K. S. Wills, C. Pilch, A. Hyslop\",\"doi\":\"10.1109/IRPS.1986.362120\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The susceptibility of CMOS devices to latch-up becomes of greater concern as the spacing between geometries is reduced. An advanced 1 micron CMOS device is used to examine various methods of determining where on the device latch-up might occur. Two of these methods are laser induced latch-up and scanning electron microscope (SEM) microprobe. A correlation is shown between the two methods.\",\"PeriodicalId\":354436,\"journal\":{\"name\":\"24th International Reliability Physics Symposium\",\"volume\":\"4 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1986-04-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"24th International Reliability Physics Symposium\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IRPS.1986.362120\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"24th International Reliability Physics Symposium","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IRPS.1986.362120","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 4

摘要

随着几何间距的减小，CMOS器件对锁存的敏感性变得更加令人关注。先进的1微米CMOS器件用于检查各种方法来确定器件上可能发生锁存的位置。其中两种方法是激光诱导闭锁和扫描电镜(SEM)微探针。这两种方法之间存在着相关性。

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A Study of CMOS Latch-up by Laser Scanning and Voltage Contrast Techniques

The susceptibility of CMOS devices to latch-up becomes of greater concern as the spacing between geometries is reduced. An advanced 1 micron CMOS device is used to examine various methods of determining where on the device latch-up might occur. Two of these methods are laser induced latch-up and scanning electron microscope (SEM) microprobe. A correlation is shown between the two methods.

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24th International Reliability Physics Symposium

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