自对齐双大马士革建筑中的铜集成

Morand, Lermé, Palleau, Torres, Vinet, Demolliens, Ulmer, Gobil, Fayolle, Romagna, Le Bihan
{"title":"自对齐双大马士革建筑中的铜集成","authors":"Morand, Lermé, Palleau, Torres, Vinet, Demolliens, Ulmer, Gobil, Fayolle, Romagna, Le Bihan","doi":"10.1109/VLSIT.1997.623680","DOIUrl":null,"url":null,"abstract":"In this paper, we will demonstrate the compatibility of copper metallization in a Self Aligned Dual Damascene architecture with 0.18pm CMOS technology requirements. This Cu metallization has also been used, for the first time, as the fifth level of metal of a 2cm2 0.35pm microprocessor for integrability demonstration on 200\" wafers.","PeriodicalId":414778,"journal":{"name":"1997 Symposium on VLSI Technology","volume":"27 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1997-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":"{\"title\":\"Copper Integration In Self Aligned Dual Damascene Architecture\",\"authors\":\"Morand, Lermé, Palleau, Torres, Vinet, Demolliens, Ulmer, Gobil, Fayolle, Romagna, Le Bihan\",\"doi\":\"10.1109/VLSIT.1997.623680\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, we will demonstrate the compatibility of copper metallization in a Self Aligned Dual Damascene architecture with 0.18pm CMOS technology requirements. This Cu metallization has also been used, for the first time, as the fifth level of metal of a 2cm2 0.35pm microprocessor for integrability demonstration on 200\\\" wafers.\",\"PeriodicalId\":414778,\"journal\":{\"name\":\"1997 Symposium on VLSI Technology\",\"volume\":\"27 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1997-06-10\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"10\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1997 Symposium on VLSI Technology\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIT.1997.623680\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1997 Symposium on VLSI Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.1997.623680","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 10

摘要

在本文中,我们将展示铜金属化在自对准双大马士革架构中与0.18pm CMOS技术要求的兼容性。这种铜金属化也首次被用作2厘米0.35微米微处理器的第5级金属,用于在200英寸晶圆上的可集成性演示。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Copper Integration In Self Aligned Dual Damascene Architecture
In this paper, we will demonstrate the compatibility of copper metallization in a Self Aligned Dual Damascene architecture with 0.18pm CMOS technology requirements. This Cu metallization has also been used, for the first time, as the fifth level of metal of a 2cm2 0.35pm microprocessor for integrability demonstration on 200" wafers.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信