J. Hayden, M. Woo, R. Taft, P. Pelley, B. Nguyen, C. Mazure, P. Kenkare, K. Kemp, R. Subrahmanyan, A. Sitaram, J. Lin, J. Ko, C. King, C. Gunderson, H. Kirsch
{"title":"一种高性能的四孔，四层聚BiCMOS工艺，用于快速16mb ram","authors":"J. Hayden, M. Woo, R. Taft, P. Pelley, B. Nguyen, C. Mazure, P. Kenkare, K. Kemp, R. Subrahmanyan, A. Sitaram, J. Lin, J. Ko, C. King, C. Gunderson, H. Kirsch","doi":"10.1109/IEDM.1992.307483","DOIUrl":null,"url":null,"abstract":"An advanced, high-performance BiCMOS technology has been developed for fast 16Mb SRAMs. A split word-line bitcell architecture, using four levels of polysilicon and two self-aligned contacts, achieves a cell area of 8.61 mu m/sup 2/ with conventional i-line lithography and 7.32 mu m/sup 2/ with i-line phase-shift lithography. The process features PELOX isolation to provide a 1.0 mu m active pitch, MOSFET transistors designed for a 0.80 mu m gate poly pitch, a double polysilicon bipolar transistor with aggressively scaled parasitics, and a thin-film polysilicon transistor to enhance bitcell stability. A quadruple-well structure improves soft error rate (SER) and allows simultaneous optimization of MOSFET and bipolar performance,.<<ETX>>","PeriodicalId":287098,"journal":{"name":"1992 International Technical Digest on Electron Devices Meeting","volume":"42 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":"{\"title\":\"A high-performance quadruple well, quadruple poly BiCMOS process for fast 16 Mb SRAMs\",\"authors\":\"J. Hayden, M. Woo, R. Taft, P. Pelley, B. Nguyen, C. Mazure, P. Kenkare, K. Kemp, R. Subrahmanyan, A. Sitaram, J. Lin, J. Ko, C. King, C. Gunderson, H. Kirsch\",\"doi\":\"10.1109/IEDM.1992.307483\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"An advanced, high-performance BiCMOS technology has been developed for fast 16Mb SRAMs. A split word-line bitcell architecture, using four levels of polysilicon and two self-aligned contacts, achieves a cell area of 8.61 mu m/sup 2/ with conventional i-line lithography and 7.32 mu m/sup 2/ with i-line phase-shift lithography. The process features PELOX isolation to provide a 1.0 mu m active pitch, MOSFET transistors designed for a 0.80 mu m gate poly pitch, a double polysilicon bipolar transistor with aggressively scaled parasitics, and a thin-film polysilicon transistor to enhance bitcell stability. A quadruple-well structure improves soft error rate (SER) and allows simultaneous optimization of MOSFET and bipolar performance,.<<ETX>>\",\"PeriodicalId\":287098,\"journal\":{\"name\":\"1992 International Technical Digest on Electron Devices Meeting\",\"volume\":\"42 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1900-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"8\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1992 International Technical Digest on Electron Devices Meeting\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IEDM.1992.307483\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1992 International Technical Digest on Electron Devices Meeting","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.1992.307483","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A high-performance quadruple well, quadruple poly BiCMOS process for fast 16 Mb SRAMs
An advanced, high-performance BiCMOS technology has been developed for fast 16Mb SRAMs. A split word-line bitcell architecture, using four levels of polysilicon and two self-aligned contacts, achieves a cell area of 8.61 mu m/sup 2/ with conventional i-line lithography and 7.32 mu m/sup 2/ with i-line phase-shift lithography. The process features PELOX isolation to provide a 1.0 mu m active pitch, MOSFET transistors designed for a 0.80 mu m gate poly pitch, a double polysilicon bipolar transistor with aggressively scaled parasitics, and a thin-film polysilicon transistor to enhance bitcell stability. A quadruple-well structure improves soft error rate (SER) and allows simultaneous optimization of MOSFET and bipolar performance,.<>
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