V. Kumari, Amrutamayee Nayak, K. Sehra, Mridula Gupta, M. Saxena
{"title":"基于TCAD的负栅偏置应力凹口AlGaN/GaN HEMT可靠性评估","authors":"V. Kumari, Amrutamayee Nayak, K. Sehra, Mridula Gupta, M. Saxena","doi":"10.1109/icee50728.2020.9777048","DOIUrl":null,"url":null,"abstract":"In the present work, the effect of negative gate bias induced stress on the performance of conventional and Recess Gate AlGaN/GaN HEMT has been presented using ATLAS TCAD simulation. Different device parameters have been used to investigate the influence of device parameters on the threshold voltage of the devices after applying negative gate bias induced stress. Results show that the recess gate architecture reduces the effect of negative gate bias stress due to the lower 2DEG density. Also, it is observed that, scaling down the gate length results in a significant degradation in the device pinch off voltage on subjecting it to a negative stress which is expected to be due to the presence of interface traps present in the device. The increase in gate leakage current in case of Recess gate HEMT has been lowered by using nitride layer at the drain end which also shows approximately the same device behavior after applying negative gate bias stress.","PeriodicalId":436884,"journal":{"name":"2020 5th IEEE International Conference on Emerging Electronics (ICEE)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2020-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"TCAD Based Reliability Assessment of Recess Gate AlGaN/GaN HEMT with Negative Gate Bias Induced Stress\",\"authors\":\"V. Kumari, Amrutamayee Nayak, K. Sehra, Mridula Gupta, M. Saxena\",\"doi\":\"10.1109/icee50728.2020.9777048\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In the present work, the effect of negative gate bias induced stress on the performance of conventional and Recess Gate AlGaN/GaN HEMT has been presented using ATLAS TCAD simulation. Different device parameters have been used to investigate the influence of device parameters on the threshold voltage of the devices after applying negative gate bias induced stress. Results show that the recess gate architecture reduces the effect of negative gate bias stress due to the lower 2DEG density. Also, it is observed that, scaling down the gate length results in a significant degradation in the device pinch off voltage on subjecting it to a negative stress which is expected to be due to the presence of interface traps present in the device. The increase in gate leakage current in case of Recess gate HEMT has been lowered by using nitride layer at the drain end which also shows approximately the same device behavior after applying negative gate bias stress.\",\"PeriodicalId\":436884,\"journal\":{\"name\":\"2020 5th IEEE International Conference on Emerging Electronics (ICEE)\",\"volume\":\"31 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2020-11-26\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2020 5th IEEE International Conference on Emerging Electronics (ICEE)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/icee50728.2020.9777048\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 5th IEEE International Conference on Emerging Electronics (ICEE)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/icee50728.2020.9777048","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
TCAD Based Reliability Assessment of Recess Gate AlGaN/GaN HEMT with Negative Gate Bias Induced Stress
In the present work, the effect of negative gate bias induced stress on the performance of conventional and Recess Gate AlGaN/GaN HEMT has been presented using ATLAS TCAD simulation. Different device parameters have been used to investigate the influence of device parameters on the threshold voltage of the devices after applying negative gate bias induced stress. Results show that the recess gate architecture reduces the effect of negative gate bias stress due to the lower 2DEG density. Also, it is observed that, scaling down the gate length results in a significant degradation in the device pinch off voltage on subjecting it to a negative stress which is expected to be due to the presence of interface traps present in the device. The increase in gate leakage current in case of Recess gate HEMT has been lowered by using nitride layer at the drain end which also shows approximately the same device behavior after applying negative gate bias stress.