基于LVT器件的SoC处理器内核时钟频率提高逻辑综合策略研究

Rengang Li, Tuo Li, Kai Liu, Gang Liu, Peng Yao, R. A
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摘要

随着SoC的发展,确保SoC的性能是非常必要的。因为SoC的性能取决于处理器的性能,所以处理器核心应该有足够的时钟频率。因此,研究提高处理器内核时钟频率的逻辑综合策略具有重要意义,但这属于研究空白。本文为弥合这一差距做了一些努力。具体而言,选择ARM内核作为处理器内核,并提出了基于LVT器件的逻辑综合策略来提高ARM内核的时钟频率。当约束设置中仅包含RVT器件时,逻辑合成后ARM内核的时钟频率为486MHz。由于在约束设置中引入了LVT设备,因此发生了一些关于时钟频率的变化。在引入比例为28%、43%和54%的情况下,时钟频率分别达到576MHz、697MHz和636MHz。推导出逻辑合成后的时钟频率与LVT器件的比例呈近似抛物线关系。时钟频率随LVT器件比例的增加先升高后降低。给出了这种关系产生的机理。因此,基于LVT器件的逻辑综合策略有助于提高ARM内核的时钟频率。需要注意的是,LVT设备的比例应设置在合理的策略范围内。合理的范围保证了时钟频率位于抛物线的上部。在合理的范围内,进一步考虑了功耗因素。当映射电路需要在一定程度上避免高功耗的潜在负面影响时,LVT器件的比例应接近合理范围的端点。然而,当映射电路必须追求高性能时,LVT器件的比例应该接近峰值点。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A Study of Logic Synthesis Strategy Based on LVT Devices for Increasing Clock Frequency of SoC Processor Core
With SoC becoming a prevailing trend, it is quite necessary to ensure the performance of SoC. Because the performance of SoC depends on the performance of processor, the processor core should have adequate clock frequency. Therefore, it is of great importance to investigate logic synthesis strategy for improving clock frequency of processor core, which belongs to a research gap. Some efforts have been made for bridging the gap in this paper. Specifically, the ARM core was chosen as the processor core, and logic synthesis strategy based on LVT devices was proposed to improve clock frequency of ARM core. When only RVT devices were included within constraints setting, the clock frequency of ARM core after logic synthesis was 486MHz. As LVT devices were introduced within constraints setting, some changes regarding the clock frequency happened. With the introduced proportion of 28%, 43% and 54%, the clock frequency respectively reached 576MHz, 697MHz and 636MHz. It was inferred the clock frequency after logic synthesis and proportion of LVT devices presented the approximate parabolic relationship. The clock frequency first increased and then decreased with the increase of LVT devices proportion. The mechanism for presenting such relationship was given. Therefore, logic synthesis strategy based on LVT devices contributed to increasing the clock frequency of ARM core. It should be noted that the proportion of LVT devices should be set within a reasonable scope for the strategy. The reasonable scope ensured the clock frequency to locate at the upper part of parabola. Within the reasonable scope, the factor of power consumption was further taken into consideration. When the mapped circuits needed to avoid potential negative effects of high power consumption at a certain extent, the proportion of LVT devices should be near the endpoint of reasonable scope. However, when the mapped circuits must pursue high performance, the proportion of LVT devices should be near the peak point.
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