Rengang Li, Tuo Li, Kai Liu, Gang Liu, Peng Yao, R. A
{"title":"基于LVT器件的SoC处理器内核时钟频率提高逻辑综合策略研究","authors":"Rengang Li, Tuo Li, Kai Liu, Gang Liu, Peng Yao, R. A","doi":"10.1109/ICICM50929.2020.9292201","DOIUrl":null,"url":null,"abstract":"With SoC becoming a prevailing trend, it is quite necessary to ensure the performance of SoC. Because the performance of SoC depends on the performance of processor, the processor core should have adequate clock frequency. Therefore, it is of great importance to investigate logic synthesis strategy for improving clock frequency of processor core, which belongs to a research gap. Some efforts have been made for bridging the gap in this paper. Specifically, the ARM core was chosen as the processor core, and logic synthesis strategy based on LVT devices was proposed to improve clock frequency of ARM core. When only RVT devices were included within constraints setting, the clock frequency of ARM core after logic synthesis was 486MHz. As LVT devices were introduced within constraints setting, some changes regarding the clock frequency happened. With the introduced proportion of 28%, 43% and 54%, the clock frequency respectively reached 576MHz, 697MHz and 636MHz. It was inferred the clock frequency after logic synthesis and proportion of LVT devices presented the approximate parabolic relationship. The clock frequency first increased and then decreased with the increase of LVT devices proportion. The mechanism for presenting such relationship was given. Therefore, logic synthesis strategy based on LVT devices contributed to increasing the clock frequency of ARM core. It should be noted that the proportion of LVT devices should be set within a reasonable scope for the strategy. The reasonable scope ensured the clock frequency to locate at the upper part of parabola. Within the reasonable scope, the factor of power consumption was further taken into consideration. When the mapped circuits needed to avoid potential negative effects of high power consumption at a certain extent, the proportion of LVT devices should be near the endpoint of reasonable scope. However, when the mapped circuits must pursue high performance, the proportion of LVT devices should be near the peak point.","PeriodicalId":364285,"journal":{"name":"2020 IEEE 5th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2020-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A Study of Logic Synthesis Strategy Based on LVT Devices for Increasing Clock Frequency of SoC Processor Core\",\"authors\":\"Rengang Li, Tuo Li, Kai Liu, Gang Liu, Peng Yao, R. A\",\"doi\":\"10.1109/ICICM50929.2020.9292201\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"With SoC becoming a prevailing trend, it is quite necessary to ensure the performance of SoC. Because the performance of SoC depends on the performance of processor, the processor core should have adequate clock frequency. Therefore, it is of great importance to investigate logic synthesis strategy for improving clock frequency of processor core, which belongs to a research gap. Some efforts have been made for bridging the gap in this paper. Specifically, the ARM core was chosen as the processor core, and logic synthesis strategy based on LVT devices was proposed to improve clock frequency of ARM core. When only RVT devices were included within constraints setting, the clock frequency of ARM core after logic synthesis was 486MHz. As LVT devices were introduced within constraints setting, some changes regarding the clock frequency happened. With the introduced proportion of 28%, 43% and 54%, the clock frequency respectively reached 576MHz, 697MHz and 636MHz. It was inferred the clock frequency after logic synthesis and proportion of LVT devices presented the approximate parabolic relationship. The clock frequency first increased and then decreased with the increase of LVT devices proportion. The mechanism for presenting such relationship was given. Therefore, logic synthesis strategy based on LVT devices contributed to increasing the clock frequency of ARM core. It should be noted that the proportion of LVT devices should be set within a reasonable scope for the strategy. The reasonable scope ensured the clock frequency to locate at the upper part of parabola. Within the reasonable scope, the factor of power consumption was further taken into consideration. When the mapped circuits needed to avoid potential negative effects of high power consumption at a certain extent, the proportion of LVT devices should be near the endpoint of reasonable scope. However, when the mapped circuits must pursue high performance, the proportion of LVT devices should be near the peak point.\",\"PeriodicalId\":364285,\"journal\":{\"name\":\"2020 IEEE 5th International Conference on Integrated Circuits and Microsystems (ICICM)\",\"volume\":\"8 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2020-10-23\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2020 IEEE 5th International Conference on Integrated Circuits and Microsystems (ICICM)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICICM50929.2020.9292201\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 IEEE 5th International Conference on Integrated Circuits and Microsystems (ICICM)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICICM50929.2020.9292201","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A Study of Logic Synthesis Strategy Based on LVT Devices for Increasing Clock Frequency of SoC Processor Core
With SoC becoming a prevailing trend, it is quite necessary to ensure the performance of SoC. Because the performance of SoC depends on the performance of processor, the processor core should have adequate clock frequency. Therefore, it is of great importance to investigate logic synthesis strategy for improving clock frequency of processor core, which belongs to a research gap. Some efforts have been made for bridging the gap in this paper. Specifically, the ARM core was chosen as the processor core, and logic synthesis strategy based on LVT devices was proposed to improve clock frequency of ARM core. When only RVT devices were included within constraints setting, the clock frequency of ARM core after logic synthesis was 486MHz. As LVT devices were introduced within constraints setting, some changes regarding the clock frequency happened. With the introduced proportion of 28%, 43% and 54%, the clock frequency respectively reached 576MHz, 697MHz and 636MHz. It was inferred the clock frequency after logic synthesis and proportion of LVT devices presented the approximate parabolic relationship. The clock frequency first increased and then decreased with the increase of LVT devices proportion. The mechanism for presenting such relationship was given. Therefore, logic synthesis strategy based on LVT devices contributed to increasing the clock frequency of ARM core. It should be noted that the proportion of LVT devices should be set within a reasonable scope for the strategy. The reasonable scope ensured the clock frequency to locate at the upper part of parabola. Within the reasonable scope, the factor of power consumption was further taken into consideration. When the mapped circuits needed to avoid potential negative effects of high power consumption at a certain extent, the proportion of LVT devices should be near the endpoint of reasonable scope. However, when the mapped circuits must pursue high performance, the proportion of LVT devices should be near the peak point.