{"title":"组合测试结构用于系统和随机效应及栅极电阻过程变化评估","authors":"L. Bortesi, L. Vendrame, G. Fontana","doi":"10.1109/ICMTS.2010.5466810","DOIUrl":null,"url":null,"abstract":"A powerful and compact test structure based on the combination of mosfet and resistor mismatch-like configurations is presented. This new combined solution helps to assess not only the systematic and stochastic mosfet and gate resistance electrical performance and their process variations but also the dependencies on the environment and the impact of different layout solutions.","PeriodicalId":153086,"journal":{"name":"2010 International Conference on Microelectronic Test Structures (ICMTS)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Combined test structure for systematic and stochastic mosfets and gate resistance process variation assessment\",\"authors\":\"L. Bortesi, L. Vendrame, G. Fontana\",\"doi\":\"10.1109/ICMTS.2010.5466810\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A powerful and compact test structure based on the combination of mosfet and resistor mismatch-like configurations is presented. This new combined solution helps to assess not only the systematic and stochastic mosfet and gate resistance electrical performance and their process variations but also the dependencies on the environment and the impact of different layout solutions.\",\"PeriodicalId\":153086,\"journal\":{\"name\":\"2010 International Conference on Microelectronic Test Structures (ICMTS)\",\"volume\":\"28 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2010-03-22\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2010 International Conference on Microelectronic Test Structures (ICMTS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICMTS.2010.5466810\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 International Conference on Microelectronic Test Structures (ICMTS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICMTS.2010.5466810","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Combined test structure for systematic and stochastic mosfets and gate resistance process variation assessment
A powerful and compact test structure based on the combination of mosfet and resistor mismatch-like configurations is presented. This new combined solution helps to assess not only the systematic and stochastic mosfet and gate resistance electrical performance and their process variations but also the dependencies on the environment and the impact of different layout solutions.