{"title":"低失真传输设计及在硅中间层上堆叠tsv的电学分析","authors":"C. Kuo, H. Kuo, Chen-Chao Wang","doi":"10.1109/ICEP.2016.7486892","DOIUrl":null,"url":null,"abstract":"In this paper, the performance of GSG co-planar waveguide (CPW) type transmission line on silicon interposer and stacking memories by through-silicon-vias (TSVs) are analyzed. The high conductor loss of fine lines will cause the impedance varying with frequency and make the reflection loss minor. Furthermore the flat attenuation of such fine line will result in low distortion waveforms and have better jitter performance compared to conventional wire-bonded memory stacking and PCB routing design. Both frequency and time domain are discussed and analyzed.","PeriodicalId":343912,"journal":{"name":"2016 International Conference on Electronics Packaging (ICEP)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-04-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Electrical analysis of low distortion transmission design and stacking TSVs on silicon interposer\",\"authors\":\"C. Kuo, H. Kuo, Chen-Chao Wang\",\"doi\":\"10.1109/ICEP.2016.7486892\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, the performance of GSG co-planar waveguide (CPW) type transmission line on silicon interposer and stacking memories by through-silicon-vias (TSVs) are analyzed. The high conductor loss of fine lines will cause the impedance varying with frequency and make the reflection loss minor. Furthermore the flat attenuation of such fine line will result in low distortion waveforms and have better jitter performance compared to conventional wire-bonded memory stacking and PCB routing design. Both frequency and time domain are discussed and analyzed.\",\"PeriodicalId\":343912,\"journal\":{\"name\":\"2016 International Conference on Electronics Packaging (ICEP)\",\"volume\":\"19 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-04-20\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 International Conference on Electronics Packaging (ICEP)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICEP.2016.7486892\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 International Conference on Electronics Packaging (ICEP)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICEP.2016.7486892","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Electrical analysis of low distortion transmission design and stacking TSVs on silicon interposer
In this paper, the performance of GSG co-planar waveguide (CPW) type transmission line on silicon interposer and stacking memories by through-silicon-vias (TSVs) are analyzed. The high conductor loss of fine lines will cause the impedance varying with frequency and make the reflection loss minor. Furthermore the flat attenuation of such fine line will result in low distortion waveforms and have better jitter performance compared to conventional wire-bonded memory stacking and PCB routing design. Both frequency and time domain are discussed and analyzed.
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