A. Deshpande, F. Luo, A. Iradukunda, D. Huitink, L. Boteler
{"title":"用于15kv半桥电源模块的堆叠DBC空腔基板","authors":"A. Deshpande, F. Luo, A. Iradukunda, D. Huitink, L. Boteler","doi":"10.1109/IWIPP.2019.8799077","DOIUrl":null,"url":null,"abstract":"High-voltage (3.3 – 10 kV) SiC power switching devices are on the verge of commercialization, while devices rated 15 kV and above are expected in the future. Consequently, there is an increasing demand for power modules that reliably packages them in common topologies for high-performance, while using standard manufacturing processes. This paper presents a solution to utilize direct-bonded-copper (DBC), which is a conventional low-voltage power module substrate, for highvoltage (15 kV) half-bridge power module packaging. The concept involves stacking multiple DBCs with the top-surface metallization pattern replicated on each inter-layer and the bottom-surface metallization. The consequent formation of the interlayer cavities within the stacked substrate creates a series-connected multi-layer capacitor under the DC+, DC−, and AC top-surface metallization. The multi-layer capacitors, where the DBC ceramic acts as the dielectric, equally distribute the high-voltage on the top-surface metallization across each ceramic under it. The voltage distribution enables minimization of the electric fields at the critical triple-point and within the bulk of ceramic. The proposed stacking allows bypassing the need for a voltage-clamped interlayer metallization. A multi-domain (electrical, thermal, mechanical) parametric analysis was performed to determine the number of ceramic layers and total ceramic thickness in the stack. The performed analysis qualitatively demonstrated the effectiveness of the proposed solution with an underlying trade-off.","PeriodicalId":150849,"journal":{"name":"2019 IEEE International Workshop on Integrated Power Packaging (IWIPP)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"16","resultStr":"{\"title\":\"Stacked DBC Cavitied Substrate for a 15-kV Half-bridge Power Module\",\"authors\":\"A. Deshpande, F. Luo, A. Iradukunda, D. Huitink, L. Boteler\",\"doi\":\"10.1109/IWIPP.2019.8799077\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"High-voltage (3.3 – 10 kV) SiC power switching devices are on the verge of commercialization, while devices rated 15 kV and above are expected in the future. Consequently, there is an increasing demand for power modules that reliably packages them in common topologies for high-performance, while using standard manufacturing processes. This paper presents a solution to utilize direct-bonded-copper (DBC), which is a conventional low-voltage power module substrate, for highvoltage (15 kV) half-bridge power module packaging. The concept involves stacking multiple DBCs with the top-surface metallization pattern replicated on each inter-layer and the bottom-surface metallization. The consequent formation of the interlayer cavities within the stacked substrate creates a series-connected multi-layer capacitor under the DC+, DC−, and AC top-surface metallization. The multi-layer capacitors, where the DBC ceramic acts as the dielectric, equally distribute the high-voltage on the top-surface metallization across each ceramic under it. The voltage distribution enables minimization of the electric fields at the critical triple-point and within the bulk of ceramic. The proposed stacking allows bypassing the need for a voltage-clamped interlayer metallization. A multi-domain (electrical, thermal, mechanical) parametric analysis was performed to determine the number of ceramic layers and total ceramic thickness in the stack. The performed analysis qualitatively demonstrated the effectiveness of the proposed solution with an underlying trade-off.\",\"PeriodicalId\":150849,\"journal\":{\"name\":\"2019 IEEE International Workshop on Integrated Power Packaging (IWIPP)\",\"volume\":\"5 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2019-04-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"16\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2019 IEEE International Workshop on Integrated Power Packaging (IWIPP)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IWIPP.2019.8799077\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 IEEE International Workshop on Integrated Power Packaging (IWIPP)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IWIPP.2019.8799077","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Stacked DBC Cavitied Substrate for a 15-kV Half-bridge Power Module
High-voltage (3.3 – 10 kV) SiC power switching devices are on the verge of commercialization, while devices rated 15 kV and above are expected in the future. Consequently, there is an increasing demand for power modules that reliably packages them in common topologies for high-performance, while using standard manufacturing processes. This paper presents a solution to utilize direct-bonded-copper (DBC), which is a conventional low-voltage power module substrate, for highvoltage (15 kV) half-bridge power module packaging. The concept involves stacking multiple DBCs with the top-surface metallization pattern replicated on each inter-layer and the bottom-surface metallization. The consequent formation of the interlayer cavities within the stacked substrate creates a series-connected multi-layer capacitor under the DC+, DC−, and AC top-surface metallization. The multi-layer capacitors, where the DBC ceramic acts as the dielectric, equally distribute the high-voltage on the top-surface metallization across each ceramic under it. The voltage distribution enables minimization of the electric fields at the critical triple-point and within the bulk of ceramic. The proposed stacking allows bypassing the need for a voltage-clamped interlayer metallization. A multi-domain (electrical, thermal, mechanical) parametric analysis was performed to determine the number of ceramic layers and total ceramic thickness in the stack. The performed analysis qualitatively demonstrated the effectiveness of the proposed solution with an underlying trade-off.